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參數(shù)資料
| 型號： | UPD61052 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER |
| 中文描述： | 馬鞍山集成電路MPEG2音頻/視頻編碼器 |
| 文件頁數(shù)： | 40/106頁 |
| 文件大?。?/td> | 824K |
| 代理商： | UPD61052 |
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Data Sheet S15082EJ4V0DS
40
μ
PD61051, 61052
3.2
3.2.1
Register Functions
Common register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
00H to 1FH
Defined by firmware
R/W
Each firmware defines these registers.
These registers are used to communicate with host CPU and internal CPU.
For the details of the register, refer to the application notebook.
The reset of the RESET pin or ALL RESET of the reset register initializes addresses 00H and 01H addresses to 0H.
The original value of the other register is unsettled. It keeps a setting value before reset.
3.2.2
Data transfer register
These registers are defined data transfer such as host CPU
→
SDRAM, SDRAM
→
host CPU, host CPU
→
iRAM
of internal CPU, SDRAM
→
iRAM of internal CPU and instruction ROM
→
iRAM of internal CPU.
The host CPU transfers with SDRAM via had a transfer buffer of 128 bytes on this LSI.
The transfer with the instruction RAM becomes 4 bytes.
A transfer error occurs if the transfer mode register, source address register, destination address register, or
transfer counter register is changed before releasing the transfer mode register following transfer completion after
setting the transfer mode register and starting the transfer. When transferring data as follows: host CPU
→
instruction
RAM of internal CPU, host CPU
→
SDRAM, SDRAM
→
instruction RAM of internal CPU, instruction ROM
→
SDRAM,
instruction ROM
→
instruction RAM of internal CPU, execute a software reset of the internal CPU (address 3EH
←
02H) before transfer and release the reset after transfer.
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