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參數(shù)資料
| 型號： | STLC5046 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 207K |
| 代理商： | STLC5046 |
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when the preamplifiergain is set 0dB or 0.66Vpp
if the gain is set to 3.52dB (MCU mode only);
higher levels must be reduced through proper di-
viders.
Typical impedanceof VFXI input is 1Mohm.
RECEIVE PATH
The received PCM signal DR through the de-
coder section, the gain select block and the D/A
converter is converted in an analog signal which
is transfered to VFRO output through an
fier stage.
In MCU mode a programmablegain block before
the A/D conversion allows to set receive gain in
12dB range, with steps <0.1dB by writing proper
code into GRXn register.
The amplifier gain can be programmed with five
different values by means of RXG Register:
0dB -1.94dB -4.44dB -7.96dB -13.98dB.
Setting GRXn=00h , the receive signal is muted
and VFRO output is set to AGND.
A/
μ
coding Law is selected by bit5 (AMU) of
CONF reg.
Setting LIN = 1 (bit6 of CONF reg.) the Linear
coding Law is selected (16bits); in this case the
signal receivedon DR will take two adjacentPCM
time slots.
in pin Strap mode only two values of Receive
Gain can be selected according to the level of
GRn control input (in Pin Strap)
GRn = 1 selects the gain correspondingto GRXn
= E2h,RXG = 0dB(-0.8dB)
GRn = 0 selects the gain correspondingto GRXn
= AFh,RXG = -1.94dB(-4.3dB)
Different gain value is obtained through proper
voltage divider.
ampli-
A/
μ
coding Law is selected according to AMU pin
level:
AMU=0
μ
-Law selected.
AMU=1
A-Lawselected.
VFRO output, referred to AGND
coupled to the load, referred to VSS, to preventa
DC current flow.
VFRO has a drive capability of
value), with a max AC swingof 2Vpp.
In order to get the best noise performances it is
recommended to keepthe GRX value as closeas
possible to the maximum (FFh) setting properly
the additional attenuationby meansof RXG.
must be AC
1.0mA (peak
PCM INTERFACE
The STLC5046 dedicate five pins (six in pin strap
mode) to the interface with the PCM highways.
MCLK represents the bit clock and is also used
by the device as a source for the clock of the in-
ternal Sigma Delta converter timings. Four possi-
ble frequencies can be used: 1.536/1.544MHz
(24 channels PCM frame); 2048MHz (32 chan-
nels PCM frame); 4.096MHz (64 channels PCM
frame); 8.192MHz (128 channels PCM frame).
The operating frequency is automatically de-
tected by the device when both MCLK and FS
are applied. MCLK is synchronizing both the
transmitdata (DX) and thereceive data (DR).
MCU mode:
The Frame Sync. signal FS is the common time
base for all the four channels; Short (one MCLK
period) or Long (more than one MCLK period)
FS areallowed.
Transmit and Receive programmable Time-Slots
are framed to an internal sync. signal that can be
coincident with FS or delayed of 1 to 7 MCLK cy-
cles depending on the programming of PCMSH
D7..................D0
D7..................D0
FS
FS
Receive TimeSlot
Transmit TimeSlot
DXAnReg.
DRAnReg.
TS0
TS23/31/61/127
Figure 3. MCU mode: Time - Slot Assignment
STLC5046
8/27
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| STLC5046S | 制造商:STMicroelectronics 功能描述:4 CHANNEL CODEC 制造商:STMicroelectronics 功能描述:4 CHANNEL CODEC - Trays |
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| STLC5048TR | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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