參數(shù)資料
型號(hào): STLC5046
廠商: 意法半導(dǎo)體
元件分類(lèi): Codec
英文描述: PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述: 可編程四通道解碼器和過(guò)濾器
文件頁(yè)數(shù): 18/27頁(yè)
文件大?。?/td> 207K
代理商: STLC5046
MCF=1: The corresponding alarm bit (CKF)
doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) gen-
erates interrupt.
Pin strap value (value=00h):
1
Loopback Register(LOOPB)
Addr=24h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DL3
DL2
DL1
DL0
AL3
AL2
AL1
AL0
DL3..0=0:Normal Operation
DL3..0=1:Codec #3..0 is set in Digital Loopback
mode, this means that the receive PCM
signal applied to the programmed
Receive Time Slot is transferredto the
programmedTransmit Time Slot.
AL3..0=0:Normal Operation
AL3..0=1:Codec #3..0 is set in AnalogLoopback
mode, this means that the VFRO signal
is tranferredto the VFXIinput internally
into the Codec.
When loopbacks are enabled the signal appears
also at the corresponding VFRO output. It is pos-
sible to have no signal on the VFRO output pro-
grammingthe GR registerto 00h in caseof digital
loopback.
Pin strap value (value=00h):
0
0
0
0
0
0
0
0
TransmitPreamplifierGain Register (TXG)
Addr=25h; Reset Value=X0h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
XG3
XG2
XG1
XG0
XG3..0=0:Transmitpreamplifiergainch.3..0= 0dB
XG3..0=1:Transmitpreamplifiergainch.3..0=3.52dB
Overall transmit gain depends on combination of
TXG and GTXn registers. For XGn=0 and
GTXn=FF 0dBm0 at DX output correspond to -
15dBm|
600
(137mVrms) at VFXI input.
Pin strap value (value=00h):
0
0
0
0
Receive Amplifier Gain Registers (RXG-10/32)
Addr: 26h; Reset Value=00h
Addr: 27h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R12
R11
R10
R02
R01
R00
R32
R31
R30
R22
R21
R20
Rn2
Rn1
Rn0
Receive Amplifier Gain
Ch#n (dB)
Mute
-13.98
-7.96
-4.44
-1.94
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Overall receive gain depends on the receive am-
plifier gain (Rn2..0 setting in RXG reg.)and
digital gain (GRXn reg. setting).
As a reference : when Rn2..0 is set for 0dB gain
and GRXn=FFh (max. gain) 0dBm0 at DR input
correspond to a level at VFRO output equal to
547mVrms (e.g. -3dBm 600ohm)
Pin strap value:
Rn2
Rn1
Rn0
GRn = 1
1
1
1
GRn = 0
1
0
0
Overall gain includingalso GRXn;
GRn = 1: -0.8dB;GRn = 0: -4.3dB.
Silicon RevisionIdentification Code (SR=D)
Addr: 31h; Read Only.
X
X
X
X
0
0
0
0
STLC5046
18/27
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