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參數資料
| 型號： | STLC5046 |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 可編程四通道解碼器和過濾器 |
| 文件頁數： | 4/27頁 |
| 文件大?。?/td> | 207K |
| 代理商： | STLC5046 |
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N.
35
38
43
46
40
Name
VFXI0
VFXI1
VFXI2
VFXI3
CAP
Type
AI
AI
AI
AI
AI
Function
TX Input Amplifier channel 0. Typ 1M
input impedance
TX Input Amplifier channel 1. Typ 1M
input impedance
TX Input Amplifier channel 2. Typ 1M
input impedance
TX Input Amplifier channel 3. Typ 1M
input impedance
AGND Voltage filter pin. A 100nF capacitor must be connected between ground and
this pin.
POWERSUPPLY
25, 36,
37, 44,
45, 56,
26,30,
31, 50,
51,55
9
8
41
VCC/0/1/2/3/
4/5
APS
Total 6 pins: 3.3V analog power supplies, should be shorted together, require 100nF
decoupling capacitor to VEE.
VEE/0/1/2/3/
4/5
APS
Total 6 pins: analog ground, should be shorted together.
VDD
VSS
SUB
DPS
DPS
DPS
Digital Power supply 3.3V, require100nF decoupling capacitor to VSS.
Digital Ground
Substrate connection. Must be shorted together with VEE and VSS pins as close as
possible the chip.
NOT CONNECTED
15, 16,
17, 18,
32, 34,
47, 49,
64
1,2,63
N.C.
Not Connected.
RES
Reserved: must be left not connected.
DIGITAL
27
M0
DI
Mode select, see M1
M1
0
1
0
1
M0
1
0
0
1
Mode Select
Pin-strap mode: Basic functions selected by proper pin strapping
MCU mode: Device controlled via serial interface
Reset status
Not Allowed
54
M1
DI
13
MCLK
DI
Master Clock Input.
Four possible frequencies can be used:
1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into and out of the DR
and DX pins.
12
TSX
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high
impedance state except when a time slot is active on the DX output. In this case TSX
output pulls low to enable the backplane line driver.
11
DX
DTO
Transmit PCM interface. It remains in high impedance state except during the
assigned time slots during wich the PCM data byte is shifted out on the rising edge of
MCLK.
10
DR
DI
Receive PCM interface. It remains inactive except during the assigned receive time
slots during which the PCM data byte is shifted in on the falling edge of MCLK.
61
IO7
DIO
Slic control I/O pin #7. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn output signalscontrolling the SLICs.
PIN DESCRIPTION
(continued)
ANALOG
STLC5046
4/27
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相關代理商/技術參數 |
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| STLC5046BCP | 制造商:STMicroelectronics 功能描述: |
| STLC5046S | 制造商:STMicroelectronics 功能描述:4 CHANNEL CODEC 制造商:STMicroelectronics 功能描述:4 CHANNEL CODEC - Trays |
| STLC5048 | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| STLC5048TR | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| STLC5411 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
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