參數(shù)資料
型號: STLC5046
廠商: 意法半導體
元件分類: Codec
英文描述: PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述: 可編程四通道解碼器和過濾器
文件頁數(shù): 16/27頁
文件大?。?/td> 207K
代理商: STLC5046
on carrying the PCM signal to be decoded and
tranferred to VFRO2 output.If linear mode is se-
lected (LIN=1 of CONF register) the 16 bits will
be used as linear code as follows: the 8most sig-
nificative bits in the programmed time slot, the 8
least significativebits in the following timeslot.
Example: if R26..R20=00:
TS0
TS1
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Pin strap value (value=80h)
1
0
0
0
0
0
0
0
Referred to FS2.
Receive Time Slot channel#3 (DRA3)
Addr=1Ah; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EN3
R36
R35
R34
R33
R32
R31
R30
EN3=0:
EN3=1:
Disablereception of selectedtime slot.
Selectedreceive timeslot on DR inputis
PCM decoded and tranferred to VFRO1
output.
R36..0:Definereceive time slot number (0 to 127)
on carrying the PCM signal to be decoded and
tranferred to VFRO2 output.If linear mode is se-
lected (LIN=1 of CONF register) the 16 bits will
be used as linear code as follows: the 8most sig-
nificative bits in the programmed time slot, the 8
least significativebits in the following timeslot.
Example: if R36..R30=00:
TS0
TS1
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Pin strap value (value=80h)
1
0
0
0
0
0
0
0
Referred to FS3.
PCM Shift Register (PCMSH)
Addr=1Bh; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
XS2
XS1
XS0
RS2
RS1
RS0
XS2..0:Effective start of the TX frame is the pro-
grammed values of clock pulses (0 to 7) after the
FS rising edge.
RS2..0:Effectivestart of the RX frame is the pro-
grammed values of clock pulses (0 to 7) after the
FS rising edge.
Pin strap value(value=00h):
0
0
0
0
0
0
0
0
Interrupt Mask Registerfor I/O port (DMASK)
Addr=1Ch; Reset Value=FFh
Addr=1Dh; Reset Value=XFh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD11 MD10 MD9
MD8
MD11..0=1: The corresponding I/O doesn’t gen-
erate interrupt.
MD11..0=0: The corresponding I/O (programmed
as Input) generate interrupt if a change of status
is detected.
Input lines with persistency check generate inter-
rupt if the changed status remains stable longer
than the
time programmed in the persistency
check registers PCHKA/B. Lines without persis-
tance check generate an immediate interrupt re-
quest.
Mask register has no effect on those pins config-
ured as outputs, those pins will not generate in-
terrupt.
Pin strap value.
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt Mask Registerfor CD port (CMASK)
Addr=1Eh; Reset Value=XFh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MC3
MC2
MC1
MC0
In MCU mode, dynamic I/O configuration, MCn
bits are the disable/enable interruptrelated to the
channel n :
MC3..0= 0 Any I/O line of the related channel is
enabled to generate interrupt depending on
DMASKsetting.
MC3..0=1
Any I/O line of the related chanel is
disabled to generate interrupt indipendently of
DMASKsetting.
In MCU mode, static I/O configuration, MCn bits
are the interrupt mask bits related to CSn that
are configuredas I/O lines.
MC3..0=1: The corresponding I/O doesn’t gener-
ate interrupt.
MC3..0=0:The correspondingI/O generateinter-
rupt if a change of statusis detected.
STLC5046
16/27
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