參數(shù)資料
型號: STLC5046
廠商: 意法半導(dǎo)體
元件分類: Codec
英文描述: PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述: 可編程四通道解碼器和過濾器
文件頁數(shù): 6/27頁
文件大?。?/td> 207K
代理商: STLC5046
N.
Name
Type
Function
28
CS0/GX0
DO/DI
MCU control mode: CS0.
Slic CS control #0.
Depending on CONF reg. content can be aCS output for SLIC #0 or a static I/O.
When configured as CS output it is automatically generated by the Codec with a
repetition time of 31.25
μ
s. In this mode also the IO
11..0
are synchronized and carry
proper data in and out synchronous with CS.
Pin-strap control mode: GX0.
Transmit gain programming channel 0:
1: Transmit gain = 0dB
0: Transmit gain = - 3.5dB
29
CS1/GX1
DO/DI
MCU control mode: CS1:
Slic CS control #1, (see CS0 description).
Pin-strap control mode: GX1.
Transmit gain programming channel 1 (see GX0 description)
53
CS2/GX2
DO/DI
MCU control mode: CS2.
Slic CS control #2, (see CS0 description).
Pin-strap control mode: GX2.
Transmit gain programming channel 2 (see GX0 description)
52
CS3/GX3
DO/DI
MCU control mode: CS3.
Slic CS control #3, (see CS0 description).
Pin-strap control mode: GX3.
Transmit gain programming channel 3 (see GX0 description)
4
CS/PD1
DI/DI
MCU control mode: CS.
Chip Select of Serial Control Bus. When this pin is low control information can be
written to or read from the device via the CI and CO pins.
Pin-strap control mode: PD1.
Power Down command channel 1. (see PD2 description).
7
CCLK/GR1
DI/DI
MCU control mode: CCLK.
Clock of Serial Control Bus. This clock shifts serial control ilnformation into or out of
CI or CO when CS input is low depending on the current instruction. CCLK may be
asyncronous with the other system clocks.
Pin-strap control mode: GR1.
Receive gain programming ch. 1, (seeGR2 description).
6
CI/PD0
DI/DI
MCU control mode: CI.
Control Data Input of Serial Control Bus. Control data is shifted in the device when
CS is low and clocked by CCLK.
Pin-strap control mode: PD0.
Power Down command channel 0. (see PD2 description).
5
CO/GR0
DTO/DI
MCU control mode: CO.
Control Data Output of Serial Control Bus. Control data is shifted out the device when
CS is low and clocked by CCLK. During the first 8 CCLK pulses the CO pin is H. I.,
valid data are shifted out during the following 8 CCLK pulses.
Pin-strap control mode: GR0.
Receive gain programming ch. 0, (seeGR2 description).
3
INT/AMU
ODO/DI MCU control mode: INT.
Interrupt output (open drain), goes low when a data change has been detected in the
I/O pins. One mask registers allow to mask any I/O pin. Interrupt is reset when the I/O
register is read.
Pin-strap control mode: AMU.
A/
μ
law selection:
AMU=0:
μ
law
AMU=1: A law, even bit inverted
PIN DESCRIPTION
(continued)
STLC5046
6/27
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