參數(shù)資料
型號： STLC5046
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述： 可編程四通道解碼器和過濾器
文件頁數(shù)： 11/27頁
文件大小： 207K
代理商： STLC5046
REGISTERSDESCRIPTION
ConfigurationRegister (CONF)
Addr=00h; Reset Value=3Fh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RES
LIN
AMU
STA
PD3
PD2
PD1
PD0
RES=0Normal Operation
RES=1 Device Reset: I/0n and CSn are all inputs,
DX is H.I.(equivalentto Hw. reset).
LIN=0
LIN=1
ment.
AMU=0
μ
law selection
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs con-
nected to the I/O control port, each CS has a
31.25
μ
s repetition time.
STA=1; I/O are static, CS0 to CS3 are config-
ured as generic staticI/O
PD3..0=0Codec 3..0 is active
PD3..0=1 Codec 3..0 is in power Down. When
one codec is in Power Down the corresponding
VFRO output is forced to AGND. and the corre-
sponding transmit time slot on DXis setin H.I.
A or
μ
law PCM encoding
Linear encoding(16 bits), two’s comple-
Pin strap value:
RES
0
AMU
0
PD3
PD2
PD1
PD0
I/ODirection Register (DIR)
Addr=01h; Reset Value=00h
Addr=02h; Reset Value=X0h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IO
7
IO
6
IO
5
IO
4
IO
3
IO
2
IO
1
IO
0
IO
11
IO
10
IO
9
IO
8
IO
11..0
= 0; I/O pin 11..0 is an input, data on the
I/Oinput is writtenin DATAn register bit 11..0.
IO
11..0
= 1; I/O pin 11..0 is an output, data con-
tained in DATAn register bit11..0 is transferred to
the I/O output.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I/OData Registerchannel #0 (DATA0)
Addr=03h;Reset Value=00h
Addr=04h;Reset Value=X0h
If bit 4 of CONFregister(STA)=0
Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D0
7
D0
6
D0
5
D0
4
D0
3
D0
2
D0
1
D0
0
D0
11
D0
10
D0
9
D0
8
When CS0 is active D0
11..0
are transferredto the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D0
11..0
will be written by
the values applied to those pins while CS0 is low.
If bit 4 of CONFregister(STA)=1
Static I/Omode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DS
7
DS
6
DS
5
DS
4
DS
3
DS
2
DS
1
DS
0
DS
11
DS
10
DS
9
DS
8
D
11..0
are transferred to the corresponding I/O
pins configuredas outputs (see DIR register). For
the I/O pins configured as inputs the correspond-
ing D
11..0
will be written by the values applied to
those pins.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
I/OData Registerchannel #1 (DATA1)
Addr=05h;Reset Value=00h
Addr=06h;Reset Value=X0h
If bit 4 of CONFregister(STA)=0
Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
D1
7
D1
6
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D1
11
D1
10
D1
9
D1
8
When CS1 is active D
11..0
are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D
11..0
will be written by
the values applied to those pins while CS1 is low.
If bit 4 of CONFregister(STA)=1
STLC5046
11/27
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