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參數(shù)資料
| 型號(hào)： | STLC5046 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 可編程四通道解碼器和過(guò)濾器 |
| 文件頁(yè)數(shù)： | 10/27頁(yè) |
| 文件大?。?/td> | 207K |
| 代理商： | STLC5046 |
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In pin-strap mode the status of the control pins is
entered at power-on reset and refreshed at any
FrameSync. cycle.
In MCU mode the control information is written to
or read from STLC5046 via the serial four wires
control bus :
CCLK : ControlClock
CS
: ChipSelect input
CI
: Serial Data input
CO
: Serial Data output
All control instructions require 2 bytes, with the ex-
ception of the single byte for command synchroni-
zation. The first byte specify the register address,
and thetypeof access(Reador Write).
The secondbyte containthe datato be loadedinto
the register (on CI wire) or carried out the register
content (on CO wire) depending on the R/W bit of
the first byte. CO wire is normally in High Imped-
ance and goes to low impedance only during the
secondbyte in caseof Readoperation.This allows
to usea commonwire forbothCI/CO.
Serial data CI is shifted to the serial input register
on the rising edge of CCLK and CO is shifted out
on the falling.
CS, normally High, is set Low during the trans-
mission / reception of a byte, lasting
pulses .
Though, in general, two bytes of the same in-
struction take
two
CS
STLC5046 can handle the data transfer in a sin-
gle 16 CCLK CS cycle,in both the directions.
One additional wire provided to the control inter-
face is an open drain interrupt output (INT) that
goes low when a change of status is detectedon
the I/O pins.
8CCLK
separated cycles
,
SLIC CONTROLINTERFACE
The device provides12 I/O pins plus4 CS signals.
The interfacecan work in dynamicor staticmode:it
canbe selectedbymeansof DIR register.
Dynamic Mode: the I/O pins are configured as
input or output by means of DIR register. The
CS signals are used to select the different SLIC
interface. In this case the I/O pin can be multi-
plexed. The data loaded from SLIC#n via I/O
pins configured as input can be read in the
DATAn register. The data written in a DATAn
registerwill be loadedon the I/O pinsconfigured
as outputwhen theCsnsignalwill be active.
Static Mode: The CS signal can be used as I/O
pins. They can be configured as input or out-
put I/O by means of DATA1 register. The data
correspondingto the CS signal can be read or
written by means of DATA2 register. All data
related to th other I/O pins can be read or writ-
ten by meansof DATA0register.
REGISTERSADDRESSES(only MCU mode)
Addr.
Name
Description
00h
01h
02h
03h
CONF
DIR-L
DIR-H
DATA0-L
Configuration Register
I/O Direction (bit 7-0)
I/O Direction (bit 11-8)
I/O Datach#0/ Static Data;
(bit 7-0)
I/O Datach#0/ Static Data ;
(bit 11-8)
I/O Datach#1 (bit 7-0) / CS
Direction
I/O Datach#1 (bit 11-8)
I/O Datach#1 (bit 7-0) / CS
Data
I/O Datach#2 (bit 11-8)
I/O Datach#3 (bit 7-0)
I/O Datach#3 (bit 11-8)
Transmit Gain ch#0
Transmit Gain ch#1
Transmit Gain ch#2
Transmit Gain ch#3
Receive Gain ch#0
Receive Gain ch#1
Receive Gain ch#2
Receive Gain ch#3
Transmit Timeslot ch#0
Transmit Timeslot ch#1
Transmit Timeslot ch#2
Transmit Timeslot ch#3
Receive Timeslot ch#0
Receive Timeslot ch#1
Receive Timeslot ch#2
Receive Timeslot ch#3
PCM Shift Register
Interrupt Mask I/O Port (03h)
Interrupt Mask I/O Port (04h)
Interrupt Mask I/O Port (07h)
Persistency Check Time for
Input A
Persistency CheckTimefor
Input B
Interrupt Register
Alarm Register
Interrupt Mask for Alarm
Loopback Register
Transmit preamp. Gain
Receive preamp. Gain(ch1 ch0)
Receive preamp. Gain(ch3 ch2)
Silicon revision identification
code
04h
DATA0-H
05h
DATA1-L
06h
07h
DATA1-H
DATA2-L
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
DATA2-H
DATA3-L
DATA3-H
GTX0
GTX1
GTX2
GTX3
GRX0
GRX1
GRX2
GRX3
DXA0
DXA1
DXA2
DXA3
DRA0
DRA1
DRA2
DRA3
PCMSH
DMASK-L
DMASK-H
CMASK
PCHK-A
20h
PCHK-B
21h
22h
23h
24h
25h
26h
27h
31h
INT
ALARM
AMASK
LOOPB
TXG
RXG-1,0
RXG-3,2
SRID
STLC5046
10/27
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