參數(shù)資料
型號(hào)： STLC5046
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述： 可編程四通道解碼器和過(guò)濾器
文件頁(yè)數(shù)： 5/27頁(yè)
文件大?。?/td> 207K
代理商： STLC5046
N.
Name
Type
Function
60
IO8
DIO
Slic control I/O pin #8. (see IO7 description).
59
IO9
DIO
Slic control I/O pin #9. (see IO7 description).
58
IO10
DIO
Slic control I/O pin #10. (see IO7 description).
57
IO11
DIO
Slic control I/O pin #11. (see IO7 description).
DIGITAL (DUAL MODE)
14
FS/FS0
DI
MCU control mode: FS.
Frame Sync. Pulse. A pulse or a squarewave waveform with an 8kHz repetition rate
is applied to this pin to define the start of the receive and transmit frame. Effective
start of the frame can be then shifted of up to 7 clock pulses indipendently in receive
and transmit directions by proper programming of the PCMSH register.
Pin-strap control mode: FS0.
Frame Sync. pulse of channel #0. One MCLK cycle long , starts PCM datatransfer in
the Time Slot following its fallingedge (Short Frame Delayed Timing).
19
IO0/GR2
DIO/DI
MCU control mode: IO0.
Slic control I/O pin #0. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn output signalscontrolling the SLICs.
Pin-strap control mode: GR2.
Receive gain programming channel 2:
1: Receive gain = = -0.8dB
0: Rec. gain = -4.3dB
20
IO1/PD2
DIO/DI
MCU control mode: IO1.
Slic control I/O pin #1. (see IO0 description).
Pin-strap control mode: PD2.
Power Down command channel 2:
1: Channel 2 Codec is in power down.
(equivalent to CONF reg bit2 = 1)
0: Channel 2 Codec is in power up.
(equivalent to CONF reg. bit2 = 0)
21
IO2/GR3
DIO/DI
MCU control mode: IO2.
Slic control I/O pin #2. (see IO0 description)
Pin-strap control mode: GR3.
Receive gain programming channel 3. (see GR2 description)
22
IO3/PD3
DIO/DI
MCU control mode: IO3.
Slic control I/O pin #3. (see IO0 description).
Pin-strap control mode: PD3.
Power Down command channel 3. (see PD2 description)
23
IO4/FS1
DIO/DI
MCU control mode: IO4
Slic control I/O pin #4. (see IO0 description).
Pin-strap control mode: FS1.
Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in
the Time Slot following its fallingedge (Short Frame Delayed Timing).
24
IO5/FS2
DIO/DI
MCU control mode: IO4.
Slic control I/O pin #5. (see IO0 description).
Pin-strap control mode: FS2.
Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in
the Time Slot following its fallingedge (Short Frame Delayed Timing).
62
IO6/FS3
DIO/DI
MCU control mode: IO4.
Slic control I/O pin #6. (see IO0 description).
Pin-strap control mode: FS3.
Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM datatransfer in
the Time Slot following its fallingedge (Short Frame Delayed Timing).
PIN DESCRIPTION
(continued)
DIGITAL
STLC5046
5/27
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