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參數(shù)資料
| 型號： | STLC5046 |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大?。?/td> | 207K |
| 代理商： | STLC5046 |
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Input lines with persistencycheck generate inter-
rupt if the changed status remains stable longer
than the
time programmend in the persistency
check registers PCHKA/B
Lines without persistency check generate an im-
mediateinterrupt request.
Mask register has no effect on those pins config-
ured as outputs, those pins will not generate in-
terrupt.
Pin strap value (value=00h):
1
1
1
1
1
1
1
1
PersistencyCheck Register (PCHK-A/B)
Two input signals per channel , labeled A and B,
are submittedto persistencycheck.
In dynamic mode (STA=0), A and B inputs of the
four channels, are sampled on the multiplexed
lines IO0 (pin13) and IO1 (pin14).
In static mode (STA=1) the persistency check is
performed on four pairs of lines, assigned to
each channelaccording to the table:
CHAN#
Input A
Input B
0
IO0 (pin 13)
IO1 (pin14)
1
IO4 (pin 17)
IO5 (pin18)
2
IO6 (pin 48)
IO7 (pin47)
3
IO10 (pin 44)
IO11 (pin 43)
Addr=1Fh;
Addr=20h;
Reset Value=00h
Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TA7..0 and TB7..0, content of PCHKA and
PCHKB registers, define the minimum duration
of input A and B to generate interrupt ; spurious
transitions shorter than the programmed value
are ignored.
The time width can be calculated according to
the formula:
Time-Width A = (TA7..0)x 64
μ
s
Time-Width B = (TB7..0)x 64
μ
s
If PCHKA/B is programmed to 00h the persist-
ency check is not performed and any detected
transitionwill generateinterrupt.
All the inputs, with or without persistency check,
are sampledwith a repetitionrate of 32
μ
s
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt Register(INT)
Addr=21h;Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ICKF
ID3
ID2
ID1
ID0
ICKF = 1: If interrupt is generatedby a changeof
bit 0 in register ALARM.
In dynamic I/O configuration
latch the interrupt request from the related chan-
nel.
Any single bit IDn is cleared after reading related
I/O register or by setting MCn bit High (i.e. when
channel n is disabled to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch
the interrupt requestfrom I/O11..0 and CS3..0re-
spectively:
ID0 : is set High when the interrupt is requested
fromany the I/O11..0lines.
ID2: is set High when the interrupt is requested
fromany of the CS3..0 (configuredas I/O).
ID0 and ID2 are cleared after reading related I/O
register.
ID1 and ID3 are don’t care.
Pin strap value(value=00b):
the ID3..0
bits
0
0
0
0
0
Alarm Register(ALARM)
Addr=22h;Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
POR
CKF
CKF=1: If
frameperiod doesnot match expectedvalue.
POR=1: If a Power On Reset is detected during
operation.
The register ALARM is cleared after reading op-
eration only if signalsare inactive.
Pin strap value(value=00h):
number of PCM clock pulses in one
0
0
Interrupt Mask Registerfor Alarm (AMASK)
Addr=23h;Reset Value=11b
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MCF
STLC5046
17/27
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