參數(shù)資料
型號(hào)： STLC5046
廠商： 意法半導(dǎo)體
元件分類(lèi)： Codec
英文描述： PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述： 可編程四通道解碼器和過(guò)濾器
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 207K
代理商： STLC5046
FUNCTIONAL DESCRIPTION
POWERON INITIALIZATION
When power is first applied it is recommended to
reset
the
device
by
M1.0=00, in order to to clear all the internal regis-
ters.
In MCU mode M0 is set steadily Low and the de-
vice is reset by applying a negative pulse to M1
(its operative level in MCU mode is High); same
result can be obtained by writing an High level
into the control bit RES of the CONF register.
In Pin-strap mode M1 is set steadily Low and the
device is reset by applying a negative pulse to
M0 (its operative levelin Pin-strap mode is High);
at the end of the Reset phase (M0=High) the de-
vice is programmed according to the logical con-
figurationof the control pins.
During the Reset condition all the I/On and CS_n
pins are set as inputs , DX is set in high imped-
anceandall VFROn outputsare forcedto AGND.
forcing
the
condition
POWERDOWN STATE
Each of the four channel may be put into power
down mode by setting the appropriate bit in the
CONF register or strapping to VDD the proper
pin. In this mode the eventual programmed DX
channel is set in high impedance while the VFRO
outputs are forced to AGND. In Pin strap mode
the value forced on the input pin is internally up-
dated everyFS signal.
TRANSMIT PATH
The analog VFXI signal through
stage is applied to a PCM converter and the cor-
an amplifier
respondingdigital signal is sent to DX output.
In MCU mode, the amplifier gain can be pro-
grammed with two different values by means of
TXG Reg. : 0dBor +3.52dB.
A programmable gain block after the A/D conver-
sion allows to set transmit gain in 12dB range,
with steps <0.1dB by writing proper code into
GTXn register.
Setting GTXn=00h , the transmitted signal is
muted, i.e. an idle PCM signal is generated on
DX.
A/
μ
coding Law is selected by bit5 (AMU) of
CONF reg.
Setting LIN=1 (bit6 of CONF reg.) the Linear cod-
ing Law is selected (16bits); in this case the sig-
nal sent on DX will take two adjacent PCM time
slots.
In Pin-strap mode, the amplifier gain is set to
0dB; only two values of Transmitgain can be se-
lected according to the level of GXn control input
(in Pin-strap):
GXn=1
selects
the
gain
GTXn=FFh (0dB)
GXn=0
selects
the
gain
GTXn=8Fh ( -3.5dB)
Different gain value is obtained through proper
voltage divider.
A/
μ
coding Law is selected according to AMU pin
level:
AMU=0
μ
-Law selected.
AMU=1
A-Lawselected.
VFXI input must be AC coupled to the signal
source; the voltage swing allowed is 1.0Vpp
corresponding
to
corresponding
to
VFRO
A/
μ
DR
GR
8 bit linear
1/4 to 1
Σ
conv.
RXG:
0dB
-1.94dB
-4.44dB
-7.96dB
-13.98dB
for RXG=0dB; GR=0dB (FF)
0dBm0 => -3dBm|
600
Figure 2. Receive path.
VFXI
TXG: 0dB
+3.52dB
1M
Σ
conv.
GX
A/
μ
8 bit linear
1/4 to 1
AGND
for TXG=0dB; GX=0dB (FF)
-15dBm|
600
0dBm0
DX
Figure 1. Transmitpath.
STLC5046
7/27
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