參數(shù)資料
型號(hào): SSTE32882HLBBKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù): 9/69頁(yè)
文件大?。?/td> 1263K
代理商: SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
17
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
DC Specifications - Voltage
The SSTE32882KA0 parametric values are specified for the device default control word settings, unless otherwise stated.
Note that the RC10 setting does not affect any of the parametric values.
Symbol
Parameter
Signals
Min
Nom
Max
Unit
VDD
DC Supply voltage (1.5V Operation)
1.425
1.5
1.575
V
DC Supply voltage (1.35V Operation)
1.282
1.35
1.451
V
VREF
DC Reference voltage
0.49 x VDD
0.50 x VDD
0.51 x VDD
V
VTT
DC Termination voltage
VREF – 40 mV
VREF
VREF + 40 mV
V
VIH(AC)
AC HIGH-level input voltage (1.5V Operation, DDR3-800/1066/1333)
Data inputs1
VREF + 175 mV
VDD + 0.4
V
AC HIGH-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
VREF + 150 mV
VDD + 0.4
V
AC HIGH-level input voltage (1.5V Operation, DDR3-1866)
Data inputs1
VREF + 135 mV
VDD + 0.4
V
AC HIGH-level input voltage (1.35V Operation, DDR3L-800/1066/1333) Data inputs1
VREF + 150 mV
VDD + 0.2
V
AC HIGH-level input voltage (1.35V Operation, DDR3L-1600)
Data inputs1
VREF + 135 mV
VDD + 0.2
V
VIL(AC)
AC LOW-level input voltage (1.5V Operation, DDR3-800/1066/1333)
Data inputs1
–0.4
VREF – 175 mV
V
AC LOW-level input voltage (1.5V Operation, DDR3-1600)
Data inputs1
–0.4
VREF – 150 mV
V
AC LOW-level input voltage (1.5V Operation, DDR3-1866)
Data inputs1
–0.4
VREF – 135 mV
V
AC LOW-level input voltage(1.35V Operation, DDR3L-800/1066/1333)
Data inputs1
–0.2
VREF – 150 mV
V
AC LOW-level input voltage (1.35V Operation, DDR3L-1600)
Data inputs1
–0.2
VREF – 135 mV
V
VIH(DC)
DC HIGH-level input voltage(1.5V Operation)
Data inputs1
VREF + 100 mV
VDD + 0.4
V
DC HIGH-level input voltage(1.35V Operation)
Data inputs1
VREF + 90 mV
VDD + 0.2
V
VIL(DC)
DC LOW-level input voltage(1.5V Operation)
Data inputs1
–0.4
VREF – 100 mV
V
DC LOW-level input voltage(1.35V Operation)
Data inputs1
–0.2
VREF – 90 mV
V
VIH(CMOS) HIGH-level input voltage
CMOS inputs2
0.65 x VDD
VDD
V
VIL(CMOS) LOW-level input voltage
CMOS inputs2
0–
0.35 x VDD
V
VIL (Static) Static LOW-level input voltage3
CK, CK,
-–
0.35 x VDD
V
VIX(AC)
Differential input crosspoint voltage range(1.5V Operation,
DDR3-800/1066/1333/1600)
CK, CK, FBIN, FBIN
0.5xVDD - 175 mV
0.5 x VDD
0.5xVDD + 175 mV
V
0.5xVDD - 200 mV4
0.5 x VDD
0.5xVDD + 200 mV4
V
Differential input crosspoint voltage range(1.5V Operation, DDR3-1866) CK, CK, FBIN, FBIN
0.5xVDD - 150 mV
0.5 x VDD
0.5xVDD + 150 mV
V
0.5xVDD - 180mV5
0.5 x VDD
0.5xVDD + 180mV4
V
Differential input crosspoint voltage range(1.35V Operation,
DDR3L-800/1066/1333/1600)
CK, CK, FBIN, FBIN
0.5xVDD - 150 mV
0.5 x VDD
0.5xVDD + 150 mV
V
0.5xVDD - 180 mV6
0.5 x VDD
0.5xVDD + 180 mV5
V
VID(AC)
Differential input voltage7 (1.5V Operation, DDR3-800/1066/1333)
CK, CK
350
VDD
mV
Differential input voltage6(1.5V Operation, DDR3-1600)
CK, CK
300
VDD
mV
Differential input voltage6(1.5V Operation, DDR3-1866)
CK, CK
270
VDD
mV
Differential input voltage6(1.35V Operation, DDR3-800/1066/1333)
CK, CK
300
VDD
mV
Differential input voltage6 (1.35V Operation, DDR3-1600)
CK, CK
270
VDD
mV
IOH
HIGH-level output current8
All outputs except ERROUT
-11
mA
IOL
LOW-level output current7
All outputs except ERROUT
11
–-
mA
IOL
LOW-level output current
ERROUT
25
mA
VOD
Differential re-driven clock swing (1.5V Operation)
Yn, Yn
500
VDD
mV
Differential re-driven clock swing (1.35V Operation)
Yn, Yn
450
VDD
mV
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