參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 56/69頁
文件大小： 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
6
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Pin Descriptions
The device has symmetric pinout with the inputs on the south side and the outputs on the east and west sides. This
allows back-to-back mounting on both sides of the PCB if more than one device is needed.
Ball Assignment: MIRROR = LOW, QCSEN = HIGH or float
This table specifies the pinout for the SSTE32882KA1 in the front configuration (QuadCS mode disabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the
device and connecting pad on the module are required in these locations. Also, balls Y2 and R6 are “do not use”
balls reserved for DCS2 and DCS3 in the QuadCS mode, and must not be connected on the system. The device is
designed to tolerate floating on these pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on
the module may be located in these areas.
1
2
345
6
7
8
9
10
11
A
QAA13
QAA8
QCSEN
VSS
RESET MIRROR ERROUT
VSS
RSVD
QBA8
QBA13
B
QAA14
QAA7
QBA7
QBA14
C
QAA9
QAA6
VDD
QBA6
QBA9
D
QAA11
QAA5
VSS
QBA5
QBA11
E
QAA2
QAA4
VDD
QBA4
QBA2
F
QAA1
QAA3
VSS
QBA3
QBA1
G
QAA0
QABA1
VDD
QBBA1
QBA0
H
QAA12
QABA0
VSS
QBBA0
QBA12
J
QABA2
QACS1
VDD
QBCS1
QBBA2
K
QAA15 QACKE0
VSS
QBCKE0
QBA15
LQAWE
QACS0
VDD
QBCS0
QBWE
M
QAA10 QACKE1
VSS
QBCKE1
QBA10
N
QACAS QAODT0
VDD
QBODT0 QBCAS
P
QARAS QAODT1
DA3
VSS
DA4
QBODT1 QBRAS
R
DCKE1
DA14
DA15
DA5
RSVD
DA2
DA1
DA10
DODT1
T
DCKE0
DCS0
DCS1
DODT0
U
DA12
DBA2
Y1
PVSS
VDD
PVDD
Y0
DA13
DCAS
V
DA9
DA11
Y1
PVSS
VSS
PVDD
Y0
DRAS
DWE
W
DA8
DA6
FBIN
Y3
AVSS
CK
RSVD
Y2
FBOUT
DA0
DBA0
Y
DA7
RSVD
FBIN
Y3
AVDD
CK
VREFCA
Y2
FBOUT
PAR_IN
DBA1
相關(guān)PDF資料
PDF描述
SSTUA32864EC,557 SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUA32866EC/G 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*