參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 43/69頁
文件大小： 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
48
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
CONTROL WORDS
The SSTE32882KA1 registers have internal control bits for adapting the configuration of certain device features.
The control bits are accessed by the simultaneous assertion of both DCS0 and DCS1 in the QuadCS disabled
mode. In the QuadCS enabled mode, the simultaneous assertion of both DCS2 and DCS3 during normal operation,
and the assertion of all four DCS[3:0] inputs also results in control word access. However, assertion of any three
DCS[3:0] inputs is not legal. Register Qn outputs including QxCKE0, QxCKE1, QxODT0 and QxODT1 remain in
their previous state. Select signals QxCS[n:0] are set to high during control word access.
The SSTE32882KA1 allocates decoding for up to 16 words of control bits, RC0 through RC15. Selection of each
word of control bits is presented on inputs DA0 through DA2 and DBA2. Data to be written into the configuration
registers need to be presented on DA3, DA4, DBA0 and DBA1. Bits DA[15:5] need to be low, and at least one
DCKEn input must be high, for valid data access. If Power Down mode is enabled in RC9[DBA1], at least one
DCKE must be high for valid control word access. The inputs on DRAS, DCAS, DWE, and DODT[1:0] can be either
high or low, and are ignored by the SSTE32882KA1 during control word access. In all cases Address and
command parity is checked during control word write operations. ERROUT is asserted and the command is ignored
if a parity error is detected. Using this mechanism, controllers may use the SSTE32882KA1 to validate the address
and command bus signal integrity to the module as long as one or more of the parity checked input signals
DA3-DA15, DBA0, DBA1, DRAS, DCAS, DWE are kept high.
Control word access must be possible at any defined frequency independent of the current setting of DBA1 control
registers.
相關(guān)PDF資料
PDF描述
SSTUA32864EC,557 SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUA32866EC/G 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*