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參數(shù)資料
| 型號： | SSTE32882HLBBKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 2/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBBKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
10
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Terminal Functions
Signal
Group
Signal Name
Type
Description
Ungated
inputs
DCKEn, DODTn
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register function pins not associated
with Chip Select.
Chip Select
gated inputs
DAn, DBAn, DRAS,
DCAS, DWE
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register inputs, re-driven only when
either chip select is LOW. If both chip selects are low the
register maintains the state of the previous input clock cycle at
its outputs
Chip Select
inputs
DCS0, DCS1
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register Chip Select signals. These pins
initiate DRAM address/command decodes, and as such
exactly one will be low when a valid address/command is
present which should be re-driven.
DCS2, DCS3
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register Chip Select signals when
QuadCS mode is enabled. DCS2 and DCS3 inputs are
disabled when QuadCS mode is disabled.
Re-driven
outputs
QxAn, QxBAn,
QxCSn, QxCKEn,
QxODTn, QxRAS,
QxCAS, QxWE
1.35V/1.5V
CMOS Outputs2
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock. x is A or B;
outputs are grouped as A or B and may be enabled or disabled
via RC0.
Parity input
PAR_IN
1.35V/1.5V
CMOS Inputs1
Input parity is received on pin PAR_IN and should maintain
parity across the Chip Select Gated inputs (see above), at the
rising edge of the input clock, one input clock cycle after
corresponding data and one or both chip selects are LOW.
Parity error
output
ERROUT
Open drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
ERROUT will be active for two clock cycles, and delayed by 3
clock cycles to the corresponding input data
Clock inputs
CK, CK
1.35V/1.5V
CMOS Inputs1
Differential master clock input pair to the PLL; has weak
internal pull-down resistors (10K
Ω~100KΩ) .
Feedback
FBIN, FBIN
1.35V/1.5V
CMOS Inputs1
Feedback clock input
Clock
FBOUT, FBOUT
1.35V/1.5V
CMOS Outputs2
Feedback clock output
Clock Outputs Yn, Yn
1.35V/1.5V
CMOS Outputs2
Re-driven Clock
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8 | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8/M | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
| SSTE32882TNA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
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