參數(shù)資料
型號(hào)： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 18/69頁(yè)
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
25
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
AC Specifications - Output Timing Requirements
Propagation Delay Timing
1 CK and Yn left out for better visibility.
2 RCA0 is re-driven command address signal based on input CA0.
Symbol
Parameter1
1
See “Qn and Yn Load Circuit” diagram.
Conditions
DDR3/DDR3L
-800/ 1066/1333
DDR3/DDR3L
-1600
DDR3-1866
Unit
Min
Max
Min
Max
Min
Max
tPDM
Propagation delay,
single-bit switching
(1.5V operation)
CK
/CK to
output2
2
See “Propagation Delay Timing” diagram below.
3tPDM range (tPDM_max - tPDM_min) must remain as 350 ps. For example, if tPDM_min for a device is 0.65 ns, it’s tPDM_max cannot
be more than 1.0 ns, If tPDM_max for a device is 1.2 ns, it’s tPDM_min cannot be less than 0.85 ns.
4
See “Voltage Waveforms Address Floating” diagram
.
0.65
1.0
0.65
1.0
0.65
1.0
ns
Propagation delay,
single-bit switching
(1.35V operation)3
0.65
1.2
0.65
1.2
tDIS
Output disable time
(1/2-Clock pre-launch)
Yn/Yn
(falling edge)
to output
float4
0.5+
tQSK1(min)
0.5+
tQSK1(min)
0.5+
tQSK1(min)
ps
Output disable time
(3/4-Clock pre-launch)
0.25+
tQSK2(min)
0.25+
tQSK2(min)
0.25+
tQSK2(min)
tEN
Output enable time
(1/2-Clock pre-launch)
Yn/Yn
(falling edge)
output
driving
0.5-
tQSK1(max)
0.5-
tQSK1(max)
0.5-
tQSK1(max)
ps
Output enable time
(3/4-Clock pre-launch)
0.75-
tQSK2(max)
0.75-
tQSK2(max)
0.75-
tQSK2(max)
CK(1)
DCS
C/A
QxCSx
Qn(C/A)
Input
Standard
C/A
Yn(1)
QxCKEx,
QxODTx
QxCSx,
QxCKEx,
QxODTx
nn+1
n+2n+3
n+4n+5
n+6
pre-
launch
CA0
3/4 Clock Qn(C/A) pre-launch time
RCA0(2)
RCA0
Yn(1)
tPDM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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