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參數(shù)資料
| 型號： | SSTE32882HLBBKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 15/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBBKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
5
Setup (tSU) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and first crossing of VIH(AC) min. Setup (tSU) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) max. If the actual signal is always
earlier than the nominal slew rate line between shaded ‘VREF(DC) to ac region’, use nominal slew rate for derating
value. If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(DC) to ac re-
gion’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value .
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Hold (tH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)MAX and the first crossing of VREF(DC). Hold (tH) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VIH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later
than the nominal slew rate line between shaded ‘dc level to VREF(DC) region’ use nominal slew rate for derating
value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(DC)
region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating
value.
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| SSTUA32866EC,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8 | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8/M | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
| SSTE32882TNA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
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