- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98142 > SSTUA32864EC,557 (NXP SEMICONDUCTORS) SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 PDF資料下載
參數(shù)資料
| 型號： | SSTUA32864EC,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 117K |
| 代理商： | SSTUA32864EC,557 |
1.
General description
The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 congurable registered buffer designed
for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout conguration of the 1 : 2 pinout from A conguration
(when LOW) to B conguration (when HIGH). The C1 input controls the pinout
conguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (oating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.
To ensure dened outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specied to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTUA32864 is available in a 96-ball, low prole ne-pitch ball grid array (LFBGA96)
package.
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM
applications
Rev. 02 — 9 March 2007
Product data sheet
相關PDF資料 |
PDF描述 |
|---|---|
| SSTUA32866EC/G | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUAF32866BHLFT | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SSTUA32864EG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V configurable registered buffer for DDR2-667 RDIMM applications |
| SSTUA32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32866BHLF | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHLFT | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHMLF | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96TFBGA - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。