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參數(shù)資料
| 型號： | SSTUA32864EC,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 117K |
| 代理商： | SSTUA32864EC,557 |
SSTUA32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
18 of 20
NXP Semiconductors
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM applications
15. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSTUA32864_2
20070309
Product data sheet
SSTUA32864_1
Modications:
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
– changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
– changed Parameter for VO to “output voltage”; moved “driver” to Conditions
– changed Parameter for IO to “output current”; moved “continuous” to Conditions
– added Vesd specications
– changed symbol “VTT” to “VT”
– Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
– IDD, supply current, static standby: changed Max value from “100 A” to “2 mA”
– Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock
only”, “per each data input, 1 ; 1 mode”, and “per each data input, 1 : 2 mode” to Conditions
– Symbol Ci: changed Parameter to “input capacitance”; moved “data inputs, CSR”,
“CK and CK”, and “RESET” to Conditions
HIGH or LOW” to Conditions
– changed Symbol “fMAX” to “fmax”
– changed Parameter for tPDM to “peak propagation delay”
– changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
– changed Parameter for tPHL to “HIGH-to-LOW propagation delay”
SSTUA32864_1
(9397 750 14757)
20050512
Product data sheet
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| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
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| SSTUAF32866BHLFT | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTUA32864EG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V configurable registered buffer for DDR2-667 RDIMM applications |
| SSTUA32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32866BHLF | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHLFT | 功能描述:IC REGIST BUFFER 25BIT DDR 96BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32866BHMLF | 制造商:Integrated Device Technology Inc 功能描述:REGISTERED BFFR SGL 25-CH CMOS 96TFBGA - Bulk |
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