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      參數(shù)資料
      型號(hào): SSTUA32864EC,557
      廠商: NXP SEMICONDUCTORS
      元件分類: 鎖存器
      英文描述: SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
      封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
      文件頁數(shù): 4/20頁
      文件大?。?/td> 117K
      代理商: SSTUA32864EC,557
      SSTUA32864_2
      NXP B.V. 2007. All rights reserved.
      Product data sheet
      Rev. 02 — 9 March 2007
      12 of 20
      NXP Semiconductors
      SSTUA32864
      1.8 V congurable registered buffer for DDR2-667 RDIMM applications
      VID = 600 mV
      Vref = 0.5VDD
      VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
      VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
      Fig 9.
      Voltage waveforms; setup and hold times
      tPLH and tPHL are the same as tPD.
      Fig 10. Voltage waveforms; propagation delay times (clock to output)
      tPLH and tPHL are the same as tPD.
      VIH =Vref + 250 mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
      VIL =Vref 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
      Fig 11. Voltage waveforms; propagation delay times (reset to output)
      tsu
      VIH
      VIL
      VID
      th
      CK
      input
      Vref
      VICR
      002aaa374
      VOH
      VOL
      output
      tPLH
      002aaa375
      VT
      VICR
      tPHL
      CK
      Vi(p-p)
      tPHL
      002aaa376
      LVCMOS
      RESET
      output
      VT
      0.5VDD
      VIH
      VIL
      VOH
      VOL
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      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
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