參數(shù)資料
型號(hào)： SSTUA32864EC,557
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù)： 2/20頁(yè)
文件大小： 117K
代理商： SSTUA32864EC,557
SSTUA32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
10 of 20
NXP Semiconductors
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM applications
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3]
Data and clock inputs must be held at valid levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 7.
Timing requirements
Recommended operating conditions; Tamb =0 °Cto+70 °C; VDD = 1.8 V ± 0.1 V; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclock
clock frequency
-
450
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
ns
tINACT
differential inputs inactive time
ns
tsu
set-up time
DCS before CK
↑, CK ↓, CSR HIGH
0.7
-
ns
DCS before CK
↑, CK ↓, CSR LOW
0.5
-
ns
CSR, ODT, CKE, and data before
CK
↑, CK ↓
0.5
-
ns
th
hold time
DCS, CSR, ODT, CKE, and data
after CK
↑, CK ↓
0.5
-
ns
Table 8.
Switching characteristics
Recommended operating conditions; Tamb =0 °Cto+70 °C; VDD = 1.8 V ± 0.1 V;
Class I, Vref =VT =VDD × 0.5 and CL = 10 pF; unless otherwise specied. See Figure 6 through Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
450
-
MHz
tPDM
peak propagation delay
CK and CK to output
[1] 1.2
-
1.8
ns
tPDMSS
simultaneous switching peak
propagation delay
CK and CK to output
-
2.0
ns
tPHL
HIGH-to-LOW propagation delay
RESET to output
-
3
ns
Table 9.
Output edge rates
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
1
-
4
V/ns
dV/dt_f
falling edge slew rate
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
-
1
V/ns
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