參數(shù)資料
型號: SSTUA32864EC,557
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù): 5/20頁
文件大?。?/td> 117K
代理商: SSTUA32864EC,557
SSTUA32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
13 of 20
NXP Semiconductors
SSTUA32864
1.8 V congurable registered buffer for DDR2-667 RDIMM applications
11.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz; Z
0 =50 ; input slew rate = 1 V/ns ± 20 %, unless otherwise specied.
(1) CL includes probe and jig capacitance.
Fig 12. Load circuit, HIGH-to-LOW slew measurement
Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, LOW-to-HIGH slew measurement
Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement
CL = 10 pF(1)
VDD
OUT
DUT
test point
RL = 50
002aaa377
VOH
VOL
output
80 %
20 %
dv_f
dt_f
002aaa378
CL = 10 pF(1)
OUT
DUT
test point
RL = 50
002aaa379
VOH
VOL
80 %
20 %
dv_r
dt_r
output
002aaa380
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