參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 48/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
52
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
CONTROL WORD FUNCTIONS
The following sections describe the contents of each control word.
RC0: Global Features Control Word
Output Inversion: When Output Inversion is disabled, all A and B output drivers of the SSTE32882KA1 are driven
to the same levels.
Output Inversion may be enabled to conserve power, reducing simultaneous switching output currents in the
SSTE32882KA1. When Output Inversion is enabled, all A outputs will follow the equivalent inputs, however the
following B outputs will be driven to the complement of the matching A output: QBA03-QBA9, QBA11, QBA13 -
QBA15, QBBA0 - QBBA2. Output Inversion does not affect SSTE32882KA1 control word programming.
Output floating refers to allowing many A/B outputs to enter a hi-Z state when they are not being used. This is to
conserve power when the outputs are resistively terminated to a voltage (e.g., VDD, VTT, or VSS). When output
floating is enabled, the following outputs (on both matching A and B outputs) are hi-Z when not actively driven:
QxAn, QxBAn, QxRAS, QxCAS, and QxWE. Output floating is independent of Output Inversion and does not affect
SSTE32882KA1 control word programming.
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x
0
Output Inversion
Output Inversion enabled
x
1
Output Inversion disabled
x
0
x
Float outputs
Float disabled
x
1
x
Float enabled
x
0
x
A outputs disabled
A outputs enabled
x
1
x
A outputs disabled
0
x
B outputs disabled
B outputs enabled
1
x
B outputs disabled
Output Inversion Functional Diagram
QAxxx output
QBxxx output
Dxxx input
RC0-DA
3
Co
nt
rol
Bit
Registe
r
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PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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