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參數(shù)資料
| 型號： | SSTE32882HLBBKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 6/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBBKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
14
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Parity, Low Power and Standby with QuadCS Mode Enabled
Inputs
Output
RESET
DCS[3:0]
CK1
1
It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic
levels (low and high) when RESET is driven high.
CK1
Σ of A/C2
2
A/C = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE. Inputs DCKE0, DCKE1, DODT0, DODT1,
DCS0 and DCS1 are not included in this range. This column represents the sum of the number of A/C
signals that are electrically high.
PAR_IN3
3
PAR_IN arrivesone clock cycle afterdata to which it applies, ERROUT is issued three clock cycles after
the failing data.
ERROUT4
4
This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ER-
ROUT is low, it stays latched low for exactly two clock cycles or until RESET is driven low.
HLXXX
XLXX
XXLX
XXXL
↑↓
Even
L
H
HLXXX
XLXX
XXLX
XXXL
↑↓
Odd
L
HLXXX
XLXX
XXLX
XXXL
↑↓
Even
H
L
HLXXX
XLXX
XXLX
XXXL
↑↓
Odd
H
HHHH
↑↓
XX
H5
5
Same three-cycle delay for ERROUT is valid for the de-select phase (see diagram)
H
XXXX
L or H
H or L
X
ERROUTn0
H
XXXX
L
X
H6
6
The system is not allowed to pull CK and CK low while ERROUT is asserted.
L
X or floating
X or floating X or floating X or floating X or floating
H
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8 | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8/M | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
| SSTE32882TNA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
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