參數(shù)資料
型號(hào)： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 4/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
12
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Function Table (Each Flip Flop) with QuadCS Mode Enabled
2
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and
HIGH) when RESET is driven HIGH.
3
ADDR = DA[15:0], DBA[2:0]
4
CMD = DRAS, DCAS, DWE.
5
CTRL = DODTn, DCKEn.
6
Qn = QxAn, QxRAS, QxCAS, QxWE, and QxBAn.
7
Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state (Q0) is maintained. Address
floating is disabled independent of control word RC0 once 3T timing is activated.
Inputs
Outputs
RESET
DCS[3:0]
CK1
1
It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic
levels (low and high) when RESET is driven high.
CK1
A/C/E2
2
A/C/E = DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, DODTn, DCKEn
Qn
QCS[3:0]
QxODTn
QxCKEn
H
LLHH
↑
↓
Control
Word
No
change
HHHH
No change No change
HHHLL
HLLLL
H
XXXX
L or H
H or L
X
No
change
No change
No change No change
HLHHH
↑↓
Dn
LHHH
DODTn
DCKEn
HHLHH
↑↓
Dn
HLHH
DODTn
DCKEn
H
HHLH
↑↓
Dn
HHLH
DODTn
DCKEn
H
HHHL
↑↓
Dn
HHHL
DODTn
DCKEn
HLHLH
↑↓
Dn
LHLH
DODTn
DCKEn
HHLLH
↑↓
Dn
HLLH
DODTn
DCKEn
HLHHL
↑↓
Dn
LHHL
DODTn
DCKEn
HHLHL
↑↓
Dn
HLHL
DODTn
DCKEn
H
XXXX
LL
X
float
L
H
HHHH
↑↓
X
No
change
or float3
3
Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state is maintained. Address
floating is disabled independent of control word RC0 once 3T timing is activated
HHHH
DODTn
DCKEn
HLLLH
↑↓
X
Ilegal Input States
HLLHL
HLHLL
H
HLLL
L
X or float
X or
float
X or
float
X or float
float
L
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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