參數(shù)資料
型號: SSTE32882HLBAKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù): 7/69頁
文件大小: 1263K
代理商: SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
15
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
PLL Function Table
Inputs
Outputs
PLL
RESET
AVDD
OEn1
1
The Output Enable (OEn) to disable the output buffer is not an input signal to the SSTE32882KA1, but an in-
ternal signal from the PLL powerdown control and test logic. It is controlled by setting or clearing the corresponding
bit in the Clock Driver mode register.
CK2
2
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels
(LOW and HIGH) when RESET is driven HIGH.
Yn
FBOUT
L
X
Float
Off
H
VDD nominal
L
H
L
HL
HOn
H
VDD nominal
L
H
L
H
L
H
L
On
H
VDD nominal
H
L
H
Float
L
HOn
H
VDD nominal
H
L
Float
H
LOn
H
VDD nominal
X
L
Float
Off
H
GND3
3
This is a device test mode and all register timing parameters are not guaranteed.
LL
H
L
HL
H
Bypassed/Off
H
LH
L
H
LH
L
Bypassed/Off
H
H
L
H
Float
L
H
Bypassed/Off
H
H
L
Float
H
L
Bypassed/Off
H
X
L
Float
Bypassed/Off
H
X
H
Reserved
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