參數(shù)資料
型號(hào)： SSTE32882HLBAKG
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 10/69頁(yè)
文件大?。?/td> 1263K
代理商： SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
18
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Voltage waveforms; input clock
VIX(AC) = 0.5XVDD±175 mV (1.5V operation) or 0.5xVDD±150 mV (1.35 V operation)
Thermal
DC Current Specifications
Operating Electrical Characteristics
VOX
Differential Output Crosspoint Voltage (1.5V Operation)
Yn, Yn
0.5xVDD – 100 mV
–
0.5xVDD + 100 mV
V
Differential Output Crosspoint Voltage (1.35V Operation)
Yn, Yn
0.5xVDD – 90 mV
–
0.5xVDD + 90 mV
V
1 DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE, PAR_IN, DCS[1:0] when QCSEN = HIGH, DCS[3:0] when QCSEN = LOW.
2 RESET, MIRROR
3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating.
4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-275 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
5 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns.
6 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH
of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns
7 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock)
8 Default settings
Symbol
Parameter
DDR3/DDR3L
-800
DDR3/DDR3L
-1066
DDR3/DDR3L-1
333
DDR3/DDR3L
-1600
DDR3-1866
Tcase (max) Case temperature1
1 Measurement procedure JESD51-2
1092
1082
1062
1032
2 This spec is meant to guarantee a Tj of 125C by the SSTE32882KA0 device. Since Tj cannot be measured or observed by users, Tcase is specified instead.
Under all thermal condition, the Tj of a SSTE32882KA0 device shall not be higher than 125 oC.
1012oC
Symbol
Parameter1
Conditions
Min
Typ2
Max
Unit
II
Input current
RESET, MIRROR, VI =VDD or GND
±5
μA
QCSEN input current
QCSEN, VI =VDD or GND
-150
5
IID
Input current
Data inputs3, VI =VDD or GND
±5
μA
CK, CK4; VI =VDD or GND
-5
150
μA
IOH
HIGH-level output current
Qn5
-11
mA
Yn, Yn, FBOUT, FBOUT
-11
mA
Symbol
Parameter
Signals
Min
Nom
Max
Unit
VIX(AC)
VID
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBAKG8 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882HLBAKG8/M 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel
SSTE32882HLBBKG 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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