參數(shù)資料
型號(hào)： SSTE32882HLBAKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 14/69頁(yè)
文件大小： 1263K
代理商： SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
21
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Timing Requirements
Symbol
Parameter
Conditions
DDR3/DDR3L-
800/ 1066/1333
DDR3/DDR3L
-1600
DDR3-1866
Unit
Min
Max
Min
Max
Min
Max
fCLOCK
Input Clock Frequency
Application Frequency1
1
All specified timing parameters apply.
300
670
300
810
300
945
MHz
fTEST
Input Clock Frequency
Test Frequency2
2
Timing parameters specified for frequency band 2 apply.
70
300
70
300
70
300
MHz
tCH/tCL
Pulse Duration, CK, CK
HIGH or LOW
0.4
tCK3
3
Clock cycle time.
tACT
Inputs active time before
RESET is taken HIGH4
4
This parameter is not necessarily production tested (see figure below).
DCKE0/1 = LOW and
DCS[n:0] = HIGH
88
8
tCK3
tMRD
Command word to
command word
programming delay
Number of clock cycles
between two command
programming accesses
88
8
tCK3
tINDIS
Input Buffers disable time
after DCKE[1:0] is LOW
DCKE[1:0] = LOW;
RESET = HIGH; CK/CK
= Toggling; RC9[DBA1] =
1 and RC9[DBA0] = 0 or
1
4
141
4
tCK3
tQDIS
Output Buffers Hi-Z after
QxCKEn is driven LOW
DCKE[1:0] = LOW;
RESET = HIGH; CK/CK
= Toggling; RC9[DBA1] =
1 and RC9[DBA0] = 0 or
1
1.5
tCK3
tCKOFF
Number of tCK required
for both DCKE0 and
DCKE1 to remain LOW
before both CK/CK are
driven low
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = Toggling
55
5
tCK3
tCKEV
Input buffers (DCKE0
and DCKE1) disable time
after CK/CK = LOW
DCKE[1:0] = LOW;
RESET = HIGH;
CK/CK = LOW
22
2
tCK3
tFixedout
puts
Static Register Output
after DCKE0 or DCKE1
is HIGH at the input (exit
from Power Saving state)
RC9[DBA1] = 1 and
RC9[DBA0] = 0 or 1
1
3
141
4
tCK3
tSU
Setup Time5
Input valid before CK/CK
100
50
40
ps
tH
Hold Time6
Input to remain valid
after CK/CK
175
125
75
ps
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBAKG8 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882HLBAKG8/M 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel
SSTE32882HLBBKG 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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