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參數(shù)資料
| 型號： | SSTE32882HLBAKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 36/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBAKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
41
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
CLOCK STOPPED POWER DOWN MODE
To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882KA1
supports a Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (VIL(static)) or float
(will eventually settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the
device stops operation and enters low-power static and standby operation. The corresponding timing are shown in
“Clock Stopped Power Down Entry and Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT
Off“. The register device will stop its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1,
which must be kept driven LOW.
The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this
state, the DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be
disabled.
Clock Stopped Power Down Mode Entry
To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power
down mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After
holding CK and CK LOW (VIL(static)) for at least one tCKEV, both CK and CK can be floated (because of the
(10K-100K Ohm) pulldown resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not
being driven).The register is now in Clock Stopped Power Down mode.
After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one tCKEV before it can float
DCKEn. At this point, all input receivers and input termination of the SSTE32882KA1 are disabled. The only active
input circuits are CK and CK, which are required to detect the wake up request from the host.
Clock Stopped Power Down Mode Exit
To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be
driven to HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can
apply a frequency and phase accurate input clock signal. Within tACT after CK and CK resumed normal operation,
the SSTE32882KA1 outputs start becoming a function of their corresponding inputs. The state of the DCS[n:0]
inputs must not be changed before the end of tSTAB. The input clock CK and CK must be stable for a time equal or
greater than tSTAB before any access to the SSTE32882KA1 can takes place.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SSTE32882HLBAKG8 | 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882HLBAKG8/M | 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel |
| SSTE32882HLBBKG | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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