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參數(shù)資料
| 型號： | SSTE32882HLBAKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大小： | 1263K |
| 代理商： | SSTE32882HLBAKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
33
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Timing of clock and data during initialization sequence with stable power
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 QxCKEn, QxODTn, QxCSn are not included in this range.
4 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
CK(1)
VDD
DCKE[0:1]
RESET
DA/C(2)
DODT[0:1]
DCS0
DCS[n:1]
PLL lock 6
μs
tACT = 8 cycles
tINIT_Power_Stable = 100 nS
Controller guarantees high logic
Controller guarantees low logic
Controller guarantees valid logic
Register proper function and timing starting from here
Register drives CKE low until ready to transfer input signals
QxCKE[0:1]
QxCS[0:1]
ERROUT
Step 0,1
Step 2
Step 3
Step 5
Step 6
Step 7
Register guarantees high logic
Step 4
Register guarantees low logic
H or L
Hi-Z
Y[0:3](1)
QxA/C(3)
Controller guarantees valid logic
H or L
QxODT[0:1]
Hi-Z
H or L
High or Low
相關(guān)PDF資料 |
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| SSTE32882HLBBKG | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| SSTUA32864EC,557 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| SSTUA32866EC/G | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBAKG8 | 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882HLBAKG8/M | 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel |
| SSTE32882HLBBKG | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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