參數(shù)資料
型號(hào)： SSTE32882HLBAKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 3/69頁(yè)
文件大?。?/td> 1263K
代理商： SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
11
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Function Table (Each Flip Flop) with QuadCS Mode Disabled
Miscellaneous
inputs
RESET
CMOS3
Active low asynchronous reset input. When LOW, it causes a
reset of the internal latches and disables the outputs, thereby
forcing the outputs to float. Once RESET becomes high the Q
outputs get enabled and are driven LOW (ERROUT is driven
high) until the first access has been performed. RESET also
resets the ERROUT signal.
MIRROR
CMOS3
Selects between two different ballouts for front or back
operation. When the MIRROR input is high, the device Input
Bus Termination (IBT) is turned off on all inputs, except the
DCSn and DODTn inputs.
QSCEN
CMOS3
Enables the QuadCS mode. The QSCEN input has a weak
internal pullup resistor (10K
Ω - 100KΩ).
Power
Vrefca1
Reference
Voltage
Input reference voltage for the differential data inputs, VDD/2
(0.75V) nominal.
Vdd
Register Power
Power supply voltage (Register)
Vss
Register Ground Ground (Register)
AVdd
Analog Power
Analog supply voltage (PLL)
AVss
Analog Ground
Analog ground (PLL)
PVdd
PLL Power
Clock logic and clock output driver power supply (PLL)
PVss
PLL Ground
Clock logic and clock output driver ground (PLL)
RSVD
I/O
Reserved pins, must be left floating (PLL)
1
1.35V/1.5V CMOS inputs use VREFCA as the switching point reference for these recievers.
2
These outputs are optimized for memory applications to drive DRAM inputs to 1.35V/1.5V signaling levels.
3
Voltage levels according standard JESD8-11A, wide range, non terminated logic.
Inputs
Outputs1
1
Q0 means the output does not change state.
RESET
DCS0
DCS1
CK2
ADDR3
CMD4
CTRL5
Qn6
QxCS0
QxCS1
QxODTn
QxCKEn
HL
L
↑↓
Control
Word
Control
Word
Control
Word
Q0
HH
Q0
HX
X
L or H H or L
X
Q0
HL
H
↑↓
XX
X
Follow
s Input
LH
Follows
Input
Follows
Input
H
X
L
X
float
L
HH
L
↑↓
XX
X
Follow
s Input
HL
Follows
Input
Follows
Input
HH
H
↑↓
X or
float
X or float
X
Q0 or
float7
HH
Follows
Input
Follows
Input
L
X or
float
X or
float
X or
float
X or
float
X or
float
X or float
X or
float
L
Signal
Group
Signal Name
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBAKG8 功能描述:寄存器 DDR3 LV REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882HLBAKG8/M 制造商:Integrated Device Technology Inc 功能描述:IC, REG 32882_LV D3-1600 176TFBGA GRN - Tape and Reel
SSTE32882HLBBKG 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Bulk 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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