參數(shù)資料
型號(hào): SSTE32882HLBAKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù): 46/69頁(yè)
文件大小: 1263K
代理商: SSTE32882HLBAKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
50
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Control Word Decoding with QuadCS Mode Disabled
Signal
Control Word Symbol
DCS0
DCS1
DBA2
DA2
DA1
DA0
Meaning
None
n/a
H
X
No control word access
None
n/a
X
H
X
No control word access
Control word 0
RC0
L
Global Features Control word
Control word 1
RC1
L
H
Clock Driver Enable Control word
Control word 2
RC2
L
H
L
Timing Control word
Control word 3
RC3
L
H
CA Signals Driver Characteristics Control word
Control word 4
RC4
L
H
L
Control Signals Driver Characteristics Control
word
Control word 5
RC5
L
H
L
H
CK Driver Characteristics Control word
Control word 6
RC6
L
H
L
Reserved, free to use by vendor
Control word 7
RC7
L
H
Reserved, free to use by vendor
Control word 8
RC8
L
H
L
Additional IBT Setting Control Word
Control word 9
RC9
L
H
L
H
Power Saving Settings Control word
Control word 10
RC10
L
H
L
H
L
Encoding for RDIMM Operating Speed
Control word 11
RC11
L
H
L
H
Encoding for RDIMM Operating VDD
Control word 12
RC12
L
H
L
Reserved for future use
Control word 13
RC13
L
H
L
H
Reserved for future use
Control word 14
RC14
L
H
L
Reserved for future use
Control word 15
RC15
L
H
Reserved for future use
相關(guān)PDF資料
PDF描述
SSTE32882HLBBKG SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
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SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
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