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參數(shù)資料
| 型號： | SSTE32882HLBAKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 24/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBAKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
30
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Clock Driver Characteristics at Test Frequency (frequency band 2)
Symbol
Parameter
Conditions
Min.
Max.
Unit
tJIT(CC)
Cycle-to-cycle period jitter
0
160
ps
tSTAB
Stabilization time
15
us
tCKSK
Total Clock Output skew1
1
This skew represents the absolute output clock skew and contains the pad skew and package skew.
100
ps
Fractional Clock Output skew2
2
This skew represents the absolute output clock skew and contains the pad skew and package skew (see “Clock
Output (Yn) Skew”). This parameter is specified for the clock pairs on each side of the register independently. The
skew is applicable to the left side of the clock pair between Y0/Y0 and Y2/Y2, as well as the right side of the clock pair
between Y1/Y1 and Y3/Y3.
TBD
tJIT(PER)
Yn Clock Period jitter
-160
160
ps
tJIT(HPER)
Half period jitter
-200
200
ps
tQSK13
3
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad
skew, clock skew, and package routing skew (see “Qn Output Skew for Standard 1/2 Clock Pre-Launch”). The output
clock jitter is not included in this skew. This parameter applies to each side of the register independently. The Qn out-
put can either be early or late.
Qn Output to clock tolerance (Standard
1/2-Clock Pre-Launch)
Output Inversion
Enabled
-100
TBD
ps
tQSK1SSO4
4
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad
skew, clock skew, and package routing skew. The output clock jitter is not included in this skew. This parameter ap-
plies to each side of the register independently. This parameter includes the skew related to Simultaneous Switching
Noise (SSO). The Qn output can either be early or late.
Output Inversion
Disabled
-100
TBD
tQSK25
5
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad
skew, clock skew, and package routing skew (see “Qn Output Skew for Standard 3/4 Clock Pre-Launch”). The output
clock jitter is not included in this skew. This parameter applies to each side of the register independently. The Qn out-
put can either be early or late.
Output clock tolerance (3/4 Clock
Pre-Launch)
Output Inversion
Enabled
-100
TBD
ps
tQSK2SSO6
6
This skew represents the absolute Qn skew compared to the output clock Yn, and contains the register pad
skew, clock skew, and package routing skew. The output clock jitter is not included in this skew. This parameter ap-
plies to each side of the register independently. This parameter includes the skew related to Simultaneous Switching
Noise (SSO). The Qn output can either be early or late.
Output Inversion
Disabled
-100
TBD
tDYNOFF
Maximum re-driven dynamic clock offset7
7 The re-driven clock signal is ideally centered in the address/control signal eye. This parameter describes the dy-
namic deviation from this ideal position including jitter and dynamic phase offset.
-500
500
ps
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