參數(shù)資料
型號(hào)： SP37E760
廠商： SMSC Corporation
英文描述： 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS
中文描述： 3.3第VI / O控制器為嵌入式應(yīng)用
文件頁(yè)數(shù)： 51/78頁(yè)
文件大?。?/td> 510K
代理商： SP37E760
SMSC DS – SP37E760
Page 51
Rev. 04/13/2001
7.3.8
CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default
value of this register after power up is 00H (Table 30). CR07 controls auto power management.
Table 30 - CR07: Auto Power Management and Boot Drive Select
BIT NO.
BIT NAME
Read as 0.
CR07
DESCRIPTION
0,1
Reserved
2
Reserved
Read as 0.
3
Reserved
Read as 0.
This bit controls the AUTOPOWER DOWN feature of the Parallel Port.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
UART 2 Enable This bit controls the AUTOPOWER DOWN feature of the UART2.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
UART 1 Enable This bit controls the AUTOPOWER DOWN feature of the UART1.
The function is:
0 = Auto powerdown disabled (default)
1 = Auto powerdown enabled
This bit is reset to the default state by POR or a hardware reset.
Reserved
Read as 0.
4
Parallel Port
Enable
5
6
7
7.3.9
CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default
value of this register after power up is 00H (Table 31). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx
address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read.
Table 31 - CR08: ADRx Lower Address Decode
D7
D6
D5
D4
ADRA7
ADRA6
ADRA5
ADRA4
CR08
D3
D2
D1
D0
Reserved
7.3.10 CR09
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default
value of this register after power up is 00H (Table 32). CR09 contains the upper 3 bits (ADRA10:8) of the ADRx
address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the
ADRx Address Decoder (Table 33).
Table 32 - CR09: ADRx Upper Address Decoder and Configuration
D7
D6
D5
D4
ADRx
CONFIGURATION
CONTROL
D3
D2
D1
D0
Reserved
ADRA10
ADRA9
ADRA8
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