參數(shù)資料
型號(hào)： SP37E760
廠商： SMSC Corporation
英文描述： 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS
中文描述： 3.3第VI / O控制器為嵌入式應(yīng)用
文件頁(yè)數(shù)： 17/78頁(yè)
文件大?。?/td> 510K
代理商： SP37E760
SMSC DS – SP37E760
Page 17
Rev. 04/13/2001
Table 5 - Interrupt Control
FIFO
MODE
ONLY
BIT
3
0
0
INTERRUPT
IDENTIFICATION
REGISTER
BIT
2
1
INTERRUPT SET AND RESET FUNCTIONS
BIT
BIT
0
1
0
PRIORITY
LEVEL
INTERRUPT
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET CONTROL
0
1
0
1
Highest
-
None
Receiver Line
Status
None
Overrun Error,
Parity Error,
Framing Error
or Break
Interrupt
Receiver Data
Available
Reading the Line
Status Register
-
0
1
0
0
Second
Received
Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Reading the
Receiver Buffer
Register
1
1
0
0
Second
Character
Time-out
Indication
No Characters
Have Been
Removed
From or Input
to the RCVR
FIFO during
the last 4
Character
times and there
is at least 1
character in it
during this time
Transmitter
Holding
Register Empty
0
0
1
0
Third
Transmitter
Holding
Register
Empty
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter Holding
Register
Reading the
MODEM Status
Register
0
0
0
0
Fourth
MODEM
Status
Clear to Send
or Data Set
Ready or Ring
Indicator or
Data Carrier
Detect
4.1.5
The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. This
register is used to enable and clear the FIFOs and set the RCVR FIFO trigger level. Note: DMA is not supported.
4.1.5.1
FIFO Enable, Bit 0
Setting the FIFO Enable bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0”
disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to
non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this
register are written to or they will not be properly programmed.
4.1.5.2
RCVR FIFO Reset, Bit 1
Setting the RCVR FIFO Reset bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic
to 0. The shift register is not cleared. This bit is self-clearing.
4.1.5.3
XMIT FIFO Reset, Bit 2
Setting the XMIT FIFO Reset bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The
shift register is not cleared. This bit is self-clearing.
FIFO CONTROL REGISTER (FCR)
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