參數(shù)資料
型號(hào)： SP37E760
廠商： SMSC Corporation
英文描述： 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS
中文描述： 3.3第VI / O控制器為嵌入式應(yīng)用
文件頁(yè)數(shù)： 48/78頁(yè)
文件大小： 510K
代理商： SP37E760
SMSC DS – SP37E760
Page 48
Rev. 04/13/2001
7.3.1
CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default
value of this register after power up is 28H (Table 25).
Table 25 - CR00
BIT NO.
BIT NAME
0:2
Reserved
Read Only. A read returns 0
3
Reserved
Read Only.
4,5,6
Reserved
Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0.
7
Valid
A high level on this software controlled bit can be used to indicate
that a valid configuration cycle has occurred. The control software
must take care to set this bit at the appropriate times. Set to zero
after power up. This bit has no effect on any other hardware in the
chip.
CR00
DESCRIPTION
7.3.2
CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default
value of this register after power up is 9CH (Table 26).
Table 26 - CR01
BIT NO.
BIT NAME
0,1
Reserved
Read Only. A read returns “0”.
2
Parallel Port
Power
A low level on this bit puts the Parallel Port in low power mode.
3
Parallel Port
Mode
Printer Mode (Default). A low level on this bit enables the Extended
Parallel port modes. Refer to Bits 0 and 1 of CR4
4
Reserved
Read Only. A read returns “1”.
5,6
Reserved
Read Only. A read returns “0”.
7
Lock CRx
A high level on this bit enables the reading and writing of CR00 -
CR2F (Default). A low level on this bit disables the reading and
writing of CR00 - CR2F. Note: once the Lock Crx bit is set to “0”,
this bit can only be set to “1” by a hard reset or power-up reset.
Note
1
:
Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
CR01
DESCRIPTION
A high level on this bit, supplies power to the Parallel Port (Default).
Parallel Port Mode. A high level on this bit, sets the Parallel Port for
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