參數(shù)資料
型號: SMJ44C251B
廠商: Texas Instruments, Inc.
英文描述: 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述: 262144 4位多端口視頻內(nèi)存
文件頁數(shù): 45/53頁
文件大?。?/td> 913K
代理商: SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tap Point
A0–A8
RAS
CAS
DSF
TRG
W
SC
A0–A8
SE
Row
Don’t Care
SDQ0–SDQ3
H
L
Don’t Care
Valid In
Invalid Out
Valid Out
tc(TRD)
td(RLCL)
tw(RL)
td(RLCH)
tw(CL)
th(RLCA)
tsu(RA)
th(RA)
tsu(CA)
th(CLCA)
tsu(SFR)
tsu(TRG)
tsu(WMR)
th(RWM)
td(CLSH)
td(RLSH)
td(SCRL)
tsu(SDS)
tc(SC)
ta(SQ)
tw(RH)
th(TRG)
DQ0–DQ3
Hi-Z
QSF
Tap Point bit A7
td(CHRL)
td(RLCA)
td(CARH)
tw(GH)
td(THSC)
td(GHQSF)
td(RLQSF)
td(CLQSF)
th(SFR)
td(CLGH)
td(THRL)
td(THRH)
td(RLTH)
th(SDS)
td(SDRL)
td(CAGH)
Don’t Care
Don’t Care
NOTES: A. Late-load operation is defined as td(THRH) < 0 ns
.
B. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 33. Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode
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SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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