參數(shù)資料
型號(hào): SMJ44C251B
廠商: Texas Instruments, Inc.
英文描述: 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述: 262144 4位多端口視頻內(nèi)存
文件頁數(shù): 29/53頁
文件大?。?/td> 913K
代理商: SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
RAS
CAS
DSF
TRG
W
DQ0–
DQ3
A0–A8
td(RLCL)
tw(CL)
tw(CH)
td(CLRH)
tw(RH)
td(CHRL)
ta(CP)
td(CARH)
td(RLCH)
th(RA)
th(RLCA)
tsu(RA)
tsu(TRG)
th(RHrd)
th(CHrd)
tsu(rd)
tsu(WMR)
ta(C)
ta(CA)
ta(G)
ta(R)
ta(CP)
ta(CA)
tdis(G)
tdis(CH)
Valid Output
Row
Column
Column
th(CLCA)
th(TRG)
Don’t Care
td(CHRL)
Valid
Output
Data In
tw(TRG)
td(GLRH)
tw(TRG)
td(CLGH)
tdis(G)
ta(G)
tdis(CH)
td(DGL)
td(DCL)
tc(rdWP)
td(RLCA)
tsu(CA)
td(CLGH)
Access time is ta(CP) or ta(CA) dependent.
Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and CAS to select the desired write
mode (normal, block write, etc.)
Figure 17. Enhanced-Page-Mode Read-Cycle Timing
相關(guān)PDF資料
PDF描述
SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10HK 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10HL 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10JD 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10SV 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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