參數(shù)資料
型號： SMJ44C251B
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述： 262144 4位多端口視頻內(nèi)存
文件頁數(shù)： 13/53頁
文件大?。?/td> 913K
代理商： SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
transfer operation (continued)
As shown in Table 3, the SMJ44C251B supports five basic modes of transfer operation:
Register-to-memory transfer (normal write transfer, SAM to DRAM)
Alternate-write transfer (independent of the state of SE)
Memory-to-register transfer (pseudo-transfer write). Switches serial port from serial-out mode to serial-in
mode. No actual data transfer takes place between the DRAM and the SAM.
Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM)
Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
Table 3. Transfer-Operation Functions
FUNCTION
RAS FALL
CAS
FALL
ADDRESS
DQ0–DQ3
CAS
TRG
W
DSF
SE
DSF
RAS
CAS
RAS
CAS
W
Register-to-memory transfer
(normal write transfer)
H
L
L
X
L
X
Row
Addr
Tap
Point
X
X
Alternate-write transfer
(independent of SE)
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Serial-write-mode enable
(pseudo-transfer write)
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Memory-to-register transfer
(normal read transfer)
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Split-register-read transfer
(must reload tap)
Legend:
H = High
L = Low
X = Don’t care
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
write transfer
All write-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row
in the DRAM. To invoke a write-transfer cycle, W must be low when RAS falls. There are three possible
write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer.
All write-transfer cycles switch the serial port to the serial-in mode.
normal-write transfer (SAM-to-DRAM transfer)
A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array.
TRG, W, and SE are brought low and latched at the falling edge of RAS. Nine row-address bits (A0–A8) are
also latched at the falling edge of RAS to select one of the 512 rows available as the destination of the data
transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS to select one of the 512
tap points in SAM that are available for the next serial input.
During a write-transfer operation before RAS falls, the serial-input operation must be suspended after a
minimum delay of t
d(SCRL)
but can be resumed after a minimum delay of t
d(RHSC)
after RAS goes high
(see Figure 6).
相關(guān)PDF資料
PDF描述
SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
SMJ4C1024-10HK 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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