參數(shù)資料
型號： SMJ44C251B
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述： 262144 4位多端口視頻內(nèi)存
文件頁數(shù)： 21/53頁
文件大?。?/td> 913K
代理商： SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
’44C251B-10
MIN
190
’44C251B-12
MIN
220
UNIT
SYMBOL
MAX
MAX
tc(rd)
tc(W)
tc(rdW)
tc(P)
tc(rdWP)
tc(TRD)
tc(TW)
tc(SC)
tw(CH)
tw(CL)
tw(RH)
tw(RL)
tw(WL)
tw(TRG)
tw(SCH)
tw(SCL)
tw(SEL)
tw(SEH)
tw(GH)
tw(RL)P
tsu(CA)
tsu(SFC)
tsu(RA)
tsu(WMR)
tsu(DQR)
tsu(TRG)
tsu(SE)
tsu(SESC)
tsu(SFR)
tsu(DCL)
tsu(DWL)
tsu(rd)
tsu(WCL)
Timing measurements are referenced to VIL max and VIH min.
NOTES:
9. All cycle times assume tt = 5 ns.
10. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data
out cycle needs to be 70 ns minimum.
11. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this may require
additional CAS low time [tw(CL)].
12. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this may require
additional RAS low time [tw(RL)].
13. Register-to-memory (write) transfer cycles only
Cycle time, read (see Note 9)
tRC
tWC
tRMW
tPC
tPRMW
tRC
tWC
tSCC
tCPN
tCAS
tRP
tRAS
tWP
ns
Cycle time, write (see Note 9)
190
220
ns
Cycle time, read-modify-write (see Note 9)
250
290
ns
Cycle time, page-mode read or write (see Note 9)
60
70
ns
Cycle time, page-mode read-modify-write (see Note 9)
105
125
ns
Cycle time, read transfer (see Note 9)
190
220
ns
Cycle time, write transfer (see Note 9)
190
220
ns
Cycle time, serial clock (see Notes 9 and 10)
30
35
ns
Pulse duration, CAS high
20
30
ns
Pulse duration, CAS low (see Note 11)
25
75000
30
75000
ns
Pulse duration, RAS high
80
90
ns
Pulse duration, RAS low (see Note 12)
100
75000
120
75000
ns
Pulse duration, W low
25
25
ns
Pulse duration, TRG low
25
30
ns
Pulse duration, SC high
tSC
tSCP
tSE
tSEP
tTP
10
12
ns
Pulse duration, SC low
10
12
ns
Pulse duration, SE low
35
40
ns
Pulse duration, SE high
35
40
ns
Pulse duration, TRG high
30
30
ns
Pulse duration, RAS low (page mode)
100
75000
120
75000
ns
Setup time, column address
tASC
tFSC
tASR
tWSR
tMS
tTHS
tESR
tSWIS
tFSR
tDSC
tDSW
tRCS
tWCS
0
0
ns
Setup time, DSF before CAS low
0
0
ns
Setup time, row address
0
0
ns
Setup time, W before RAS low
0
0
ns
Setup time, DQ before RAS low
0
0
ns
Setup time, TRG before RAS low
0
0
ns
Setup time, SE before RAS low (see Note 13)
0
0
ns
Setup time, serial write disable
10
15
ns
Setup time, DSF before RAS low
0
0
ns
Setup time, data before CAS low
0
0
ns
Setup time, data before W low
0
0
ns
Setup time, read command
0
0
ns
Setup time, early write command before CAS low
0
0
ns
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