參數(shù)資料
型號(hào)： SMJ44C251B
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述： 262144 4位多端口視頻內(nèi)存
文件頁數(shù)： 23/53頁
文件大?。?/td> 913K
代理商： SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’44C251B-10
MIN
’44C251B-12
MIN
UNIT
SYMBOL
MAX
MAX
td(RLCH)RF
td(CLRL)RF
td(RHCL)RF
td(CLGH)
td(GHD)
Delay time, RAS low to CAS high (see Note 20)
tCHR
tCSR
tRPC
25
25
ns
Delay time, CAS low to RAS low (see Note 20)
10
10
ns
Delay time, RAS high to CAS low (see Note 20)
10
10
ns
Delay time, CAS low to TRG high for DRAM read cycles
25
30
ns
Delay time, TRG high before data applied at DQ
tOED
25
30
ns
td(RLTH)
Delay time, RAS low to TRG high (real-time-reload read-transfer cycle
only)
tRTH
90
95
ns
td(RLSH)
td(CLSH)
td(SCTR)
td(THRH)
Delay time, RAS low to first SC high after TRG high (see Note 21)
tRSD
tCSD
tTSL
tTRD
130
140
ns
Delay time, CAS low to first SC high after TRG high (see Note 21)
40
45
ns
Delay time, SC high to TRG high (see Notes 21, 22, and 23)
15
20
ns
Delay time, TRG high to RAS high (see Notes 22 and 23)
–10
–10
ns
td(SCRL)
Delay time, SC high to RAS low with TRG = W = low
(see Notes 13, 24, and 25)
tSRS
10
20
ns
td(SCSE)
td(RHSC)
td(THRL)
td(THSC)
td(SESC)
Delay time, SC high to SE high in serial-input mode
20
20
ns
Delay time, RAS high to SC high (see Note 13)
tSRD
tTRP
tTSD
tSWS
25
30
ns
Delay time, TRG high to RAS low (see Note 26)
tw(RH)
35
tw(RH)
40
ns
Delay time, TRG high to SC high (see Notes 22 and 23)
ns
Delay time, SE low to SC high (see Note 27)
10
15
ns
td(RHMS)
Delay time, RAS high to last (most significant) rising edge of SC before
boundary switch during split-register read-transfer cycles
15
20
ns
td(CLGH)
td(CASH)
Delay time, CAS low to TRG high in real-time read-transfer cycles
tCTH
tASD
5
5
ns
Delay time, column address to first SC in early-load read-transfer cycles
45
50
ns
td(CAGH)
Delay time, column address to TRG high in real-time read-transfer
cycles
tATH
10
10
ns
td(RLCA)
td(DCL)
td(DGL)
td(RLSD)
td(GLRH)
Timing measurements are referenced to VIL max and VIH min.
NOTES: 13. Register-to-memory (write) transfer cycles only
19. The maximum value is specified only to assure RAS access time.
20. CAS-before-RAS refresh operation only
21. Early-load read-transfer cycle only
22. Real-time-reload read-transfer cycle only
23. Late-load read-transfer cycle only
24. In a read-transfer cycle, the state of SC when RAS falls is a don’t care condition. However, to assure proper sequencing of the internal
clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
25. In a memory-to-register (read) transfer cycle, td(SCRL) applies only when the SAM was previously in serial-input mode.
26. Memory-to-register (read) and register-to-memory (write) transfer cycles only
27. Serial data-in cycles only
Delay time, RAS low to column address (see Note 19)
tRAD
tDZC
tDZO
tSDD
tROH
15
50
15
60
ns
Delay time, data to CAS low
0
0
ns
Delay time, data to TRG low
0
0
ns
Delay time, RAS low to serial-input data
50
50
ns
Delay time, TRG low to RAS high
25
30
ns
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