參數(shù)資料
型號: SMJ44C251B
廠商: Texas Instruments, Inc.
英文描述: 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述: 262144 4位多端口視頻內(nèi)存
文件頁數(shù): 31/53頁
文件大?。?/td> 913K
代理商: SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
5
Valid
Out
ta(G)
RAS
CAS
W
DQ0–DQ3
TRG
A0–A8
Row
Column
1
2
2
Column
3
4
5
Valid
Out
tw(RL)P
td(RLCH)
tc(rdWP)
tw(CL)
td(RLCL)
tw(CH)
td(CLRH)
td(CHRL)
tw(RH)
tsu(RA)
tsu(SFR)
th(SFR)
tsu(SFC)
th(SFC)
tsu(SFC)
th(SFC)
td(DCL)
tsu(WRH)
tw(WL)
td(CLWL)
td(CAWL)
td(RLWL)
tsu(rd)
tsu(WMR)
ta(C)
ta(CA)
tsu(DWL)
tsu(DQR)
th(TRG)
ta(R)
td(GHD)
tdis(G)
DSF
tsu(CA)
th(RLCA)
th(RA)
td(CHRL)
td(RLCA)
th(CLCA)
td(CARH)
td(CLGH)
tsu(TRG)
th(RDQ)
td(CLGH)
tw(TPG)
tsu(WCH)
th(RWM)
td(DCL)
tw(TRG)
th(WLD)
tsu(DWL)
td(GHD)
th(WLD)
ta(CP)
ta(C)
td(DGL)
td(DGL)
Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
Figure 19. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 8. Write-Cycle State Table
CYCLE
STATE
3
H
1
L
2
L
4
5
Write operation
Don’t care
Valid data
Write-mask load/use, write DQs to I/Os
L
L
L
Write mask
Valid data
Use previous write mask, write DQs to I/Os
H
L
L
Don’t care
Valid data
Load write mask on later of W fall and CAS fall
H
L
H
Don’t care
Write mask
相關(guān)PDF資料
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SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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