參數(shù)資料
型號(hào): SMJ44C251B
廠商: Texas Instruments, Inc.
英文描述: 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述: 262144 4位多端口視頻內(nèi)存
文件頁數(shù): 36/53頁
文件大?。?/td> 913K
代理商: SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A8
W
TRG
DSF
DQ0–DQ3
tw(RL)P
td(RLCH)
td(RLCL)
tw(CL)
tw(CH)
tc(P)
td(CLRH)
td(CHRL)
tw(RH)
tsu(RA)
th(RA)
tsu(CA)
th(CLCA)
td(CARH)
2
tsu(WMR)
th(RWM)
tsu(SFR)
th(SFR)
th(SFC)
tsu(SFC)
th(SFC)
tsu(WCH)
tw(WL)
tsu(WCH)
tsu(WRH)
tsu(DQR)
th(RDQ)
tsu(DWL)
tsu(DCL)
th(CLD)
th(WLD)
th(RLD)
Row
Block Address
A2–A8
3
4
4
Block Address
A2–A8
th(TRG)
tsu(TRG)
See Note A
td(RLCA)
td(CHRL)
th(RLCA)
tsu(SFC)
1
Referenced to CAS or W, whichever occurs last
NOTE A: TRG must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If
the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS.
Figure 24. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 11. Enhanced-Page-Mode Block-Write-Cycle Table
CYCLE
STATE
1
L
2
L
3
4
Write-mask load/use, block write
Write mask
Column mask
Use previous write mask, block write
H
L
Don’t care
Column mask
Write mask disabled, block write to all I/Os
L
H
Don’t care
Column mask
Write mask data
0: I/O write disable
1: I/O write enable
Column mask data DQn =
0 column write disable
1 column write enable
(n = 0, 1, 2, 3)
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
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SMJ4C1024-10HJ 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY
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