參數(shù)資料
型號： SMJ44C251B
廠商： Texas Instruments, Inc.
英文描述： 262144 BY 4-BIT MULTIPORT VIDEO RAM
中文描述： 262144 4位多端口視頻內(nèi)存
文件頁數(shù)： 22/53頁
文件大?。?/td> 913K
代理商： SMJ44C251B
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
’44C251B-10
MIN
’44C251B-12
MIN
UNIT
SYMBOL
MAX
MAX
tsu(WCH)
tsu(WRH)
tsu(SDS)
th(CLCA)
th(SFC)
th(RA)
th(TRG)
th(SE)
th(RWM)
th(RDQ)
th(SFR)
th(RLCA)
th(CLD)
th(RLD)
th(WLD)
th(CHrd)
th(RHrd)
th(CLW)
th(RLW)
th(WLG)
th(SDS)
th(SHSQ)
th(RSF)
th(SCSE)
td(RLCH)
td(CHRL)
td(CLRH)
td(CLWL)
td(RLCL)
td(CARH)
td(RLWL)
td(CAWL)
Timing measurements are referenced to VIL max and VIH min.
NOTES: 13. Register-to-memory (write) transfer cycles only
14. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
15. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
16. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
17. Read-modify-write operation only
18. TRG must disable the output buffers prior to applying data to the DQ terminals.
19. The maximum value is specified only to assure RAS access time.
Setup time, write before CAS high
tCWL
tRWL
tSDS
tCAH
tCFH
tRAH
tTLH
tREH
tRWH
tMH
tRFH
tAR
tDH
tDHR
tDH
tRCH
tRRH
tWCH
tWCR
tOEH
tSDH
tSOH
tFHR
tSWIH
tCSH
tCRP
tRSH
tCWD
tRCD
tRAL
tRWD
tAWD
25
30
ns
Setup time, write before RAS high with TRG = W = low
25
30
ns
Setup time, SDQ before SC high
0
0
ns
Hold time, column address after CAS low
20
20
ns
Hold time, DSF after CAS low
20
20
ns
Hold time, row address after RAS low
15
15
ns
Hold time, TRG after RAS low
15
15
ns
Hold time, SE after RAS low with TRG = W = low (see Note 13)
15
15
ns
Hold time, write mask, transfer enable after RAS low
15
15
ns
Hold time, DQ after RAS low (write-mask operation)
15
15
ns
Hold time, DSF after RAS low
15
15
ns
Hold time, column address after RAS low (see Note 14)
45
45
ns
Hold time, data after CAS low
20
25
ns
Hold time, data after RAS low (see Note 14)
45
50
ns
Hold time, data after W low
20
25
ns
Hold time, read after CAS high (see Note 15)
0
0
ns
Hold time, read after RAS high (see Note 15)
10
10
ns
Hold time, write after CAS low
30
35
ns
Hold time, write after RAS low (see Note 14)
50
55
ns
Hold time, TRG after W low (see Note 16)
25
30
ns
Hold time, SDQ after SC high
5
5
ns
Hold time, SDQ after SC high
5
5
ns
Hold time, DSF after RAS low
45
45
ns
Hold time, serial-write disable
20
20
ns
Delay time, RAS low to CAS high
100
120
ns
Delay time, CAS high to RAS low
0
0
ns
Delay time, CAS low to RAS high
25
30
ns
Delay time, CAS low to W low (see Notes 17 and 18)
55
65
ns
Delay time, RAS low to CAS low (see Note 19)
25
75
25
90
ns
Delay time, column address to RAS high
50
60
ns
Delay time, RAS low to W low (see Note 17)
130
155
ns
Delay time, column address to W low (see Note 17)
85
100
ns
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