參數(shù)資料
型號： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 86/88頁
文件大小： 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Data Sheet
9.2 I
2
C Operation
The SiI3124 provides a Multimaster I
2
C interface. For Auto-initialization of some PCI Configuration registers an external 256-
byte EEPROM memory device may be connected to this I
C interface (see section 6). Two registers are provided for
programmed read/write access to the I
C interface: the I
C Address register and the I
C Data/Control register.
9.2.1.1 I
2
C Write Operation
Verify that I
2
C Data/Control register bit 31 (I
2
C Access Start) is zero. The bit is one when an access is in progress. It is
zero when the access is complete and another operation may be started.
Write ‘1’ to clear bit 28 in the I
2
C Data/Control register. This bit is set if an error occurred during a previous access.
Program the write address for the access in the I
2
C Address register.
Program the write data for the access in the I
2
C Data/Control register (bits 7:0).
Write zero to bit 24 (I
2
C Access Type) in the I
2
C Address register.
Initiate the I
2
C write by setting bit 31 (I
2
C Access Start) in the I
2
C Data/Control register.
Poll bit 31 in the I
2
C Data/Control register. The bit is one while an access is in progress. It becomes zero when the access
completes. (Alternatively, the I
C Interrupt may be enabled. See the Global Control register and Global Interrupt Status
register descriptions on page 61.)
Check bit 28 in the I
2
C Data/Control register. The bit is set if an error occurred during the access.
9.2.1.2 I
2
C Read Operation
Verify that I
2
C Data/Control register bit 31 (I
2
C Access Start) is zero. The bit is one when an access is in progress. It is
zero when the access is complete and another operation may be started.
Write ‘1’ to clear bit 28 in the I
2
C Data/Control register. The bit is set if an error occurred during a previous access.
Program the read address for the access in the I
2
C Address register.
Write one to bit 24 (I
2
C Access Type) in the I
2
C Address register.
Initiate the I
2
C read by setting bit 31 (I
2
C Access Start) in the I
2
C Data/Control register.
Poll bit 31 in the I
2
C Data/Control register. The bit is one while an access is in progress. It becomes zero when the access
completes. (Alternatively, the I
2
C Interrupt may be enabled. See the Global Control register and Global Interrupt Status
register descriptions on page 61.)
Check bit 28 in the I
2
C Data/Control register. The bit is set if an error occurred during the access.
Read the data from bits 7:0 in the I
2
C Data/Control register.
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
86
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