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參數(shù)資料
| 型號： | SII3124A |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PCI-X to Serial ATA Controller |
| 中文描述： | PCI - X到串行ATA控制器 |
| 文件頁數(shù)： | 37/88頁 |
| 文件大?。?/td> | 621K |
| 代理商： | SII3124A |
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PCI-X to Serial ATA Controller
Silicon Image, Inc.
5.3.10 External Command PRB Structure
An external command PRB is indicated by setting control_external_command (control field, bit 2). External commands
execute in a manner similar to standard commands except that the initial command FIS is fetched from host memory instead
of the PRB FIS area. By default, an external command uses the “transparent” protocol. That is, the command will be
terminated immediately following the successful transmission of the external command FIS. If this is not the desired protocol,
the host driver can set control_protocol_override (control field, bit 0) and place the desired protocol in the Protocol Override
field (offset 0x00, bits [31:16]).
The external command FIS length may be any size (up to the 8K SATA limit) and will be automatically padded to a Dword
boundary. The SiI3124 will frame the FIS, adding SOF, EOF, and CRC. The host memory FIS image must contain the FIS
header (FIS Type, PMP, etc.). The PRB PMP field (offset 0x08, bits [11:8]) must be populated to direct the FIS to the desired
port multiplier port, or must be zero if no port multiplier is attached. For port multiplier applications, it is important that the PMP
field in the host-resident FIS and the PRB match for proper operation.
The location of the external command FIS is defined in additional SGEs with the XCF bit (SGE offset 0x0c, bit 28) set to one.
Any type of command may be sent using an external command, including commands that have associated data transfers.
Data transfer host memory locations are defined in SGEs with the XCF bit (SGE offset 0x0c, bit 28) set to zero. SGEs used to
define the external command FIS and SGEs used to define data transfer may be freely mixed in any order. The presence or
absence of the XCF bit informs the SiI3124 whether an SGE should be used for the current transfer operation.
31
Protocol Override
Received Transfer Count
Reserved
Reserved – Must Be Zero
SGE0 Data Address Low
SGE0 Data Address High
SGE0 Data Count
SGE0 TRM
SGE0 LNK
SGE0 DRD
SGE0 XCF
SGE1 Data Address Low
SGE1 Data Address High
SGE1 Data Count
SGE1 TRM
SGE1 LNK
SGE1 DRD
SGE1 XCF
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
37
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Control
PMP
Reserved
Reserved[27:0]
Reserved[27:0]
Table 5-9 Port Request Block For External Commands
相關PDF資料 |
PDF描述 |
|---|---|
| SiI3124ACBHU | PCI-X to Serial ATA Controller |
| SII3132 | PCI Express to 2-Port Serial ATA II Host Controller |
| SII3512 | PCI to Serial ATA Controller |
| SiI3512ECTU128 | PCI to Serial ATA Controller |
| SII3531A | PCI Express to Serial ATA Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
| SII3512 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI to Serial ATA Controller |
| SII3512ECTU128 | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 128-Pin TQFP 制造商:Silicone Image 功能描述: |
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