參數(shù)資料
型號(hào)： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 72/88頁
文件大小： 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Data Sheet
7.3.7 Port Interrupt Enable Set / Port Interrupt Enable Clear
Address Offset: 1010
H
/ 1014
H
Access Type: Read/Write 1 Set/Write 1 Clear
Reset Value: 0x0000_0000
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
72
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
I
S
Reserved
S
Reserved
D
U
C
P
P
P
C
C
The Interrupt Enable register is controlled by these registers. Writing to the Interrupt Enable Set register sets the Interrupt
Enable bits; the enable bit is set for each corresponding bit to which a 1 is written. Writing to the Interrupt Enable Clear
register clears the Interrupt Enable bits; the enable bit is cleared for each corresponding bit to which a 1 is written. The
Interrupt Enable register may be read at either address offset.
Note that bits 8, 9, and 10 do not have an enable bit; the corresponding interrupts are enabled by corresponding threshold
registers.
Bit [31:30]
: Interrupt Steering (R/W). This bit field specifies which one of the four interrupt lines is to be used for
interrupts from this port. INTA# is selected by 00
B
; INTB# by 01
B
; INTC# by 10
B
; and INTD# by 11
B
.
Bit [29:12,10:8]
: Reserved (R). These bits are reserved and return zeros on a read.
Bit [11,7:0]
: Interrupt Enables (R/W1S/W1C). These bits are the interrupt enables for the corresponding bits of
the Interrupt Status register.
7.3.8 32-bit Activation Upper Address
Address Offset: 101C
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Upper Address
This register contains the 32-bit value written to the upper half of the Command Activation register when the lower half of that
register is written and the 32-bit Activation control bit (bit 10) is set in the Port Control register.
7.3.9 Port Command Execution FIFO
Address Offset: 1020
H
Access Type: Read/Write
Reset Value: 0x0000_00XX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Execution Slot
Number
When written, this register causes the supplied slot number to be pushed into the tail of the command execution FIFO. A valid
PRB must be populated in the associated slot in port LRAM. When read, this register supplies the entry at the head of the
command execution FIFO. The FIFO is not popped as a result of a read operation.
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