參數(shù)資料
型號(hào)： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁(yè)數(shù)： 67/88頁(yè)
文件大小： 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Silicon Image, Inc.
7.3 Internal Register Space – Base Address 1
These registers are 32 bits wide and are the Port Registers and LRAM of the SiI3124. Access to these registers is through the
PCI Memory space. Register descriptions that follow specify the address offset for Port 0; subsequent port registers are at
2000
H
offset increments, i.e., the upper 2 bits of the 15-bit address offset is the Port number (0-3).
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
67
Address Offset
000
H
-F7F
H
F80
H
-FFF
H
1000
H
1004
H
1008
H
100C
H
1010
H
1014
H
1018
H
101C
H
1020
H
1024
H
1028
H
102C
H
1030
H
-103F
H
1040
H
1044
H
1048
H
104C
H
1050
H
1054
H
-17FF
H
1800
H
1804
H
-1BFF
H
1C00
H
-1CF7
H
1CF8
H
-1E03
H
1E04
H
1E08
H
-1EFF
H
1F00
H
1F04
H
1F08
H
1F0C
H
1F10
H
-1FFF
H
2000
H
-3FFF
H
4000
H
-5FFF
H
6000
H
-7FFF
H
Register Name
Port 0 LRAM Slots
Port Multiplier Device Status/QActive Registers
Write: Port 0 Control Set / Read: Port 0 Status
Write: Port 0 Control Clear
Port 0 Interrupt Status
Reserved
Port 0 Interrupt Enable Set
Port 0 Interrupt Enable Clear
Reserved
32-bit Activation Upper Address
Port 0 Command Execution FIFO
Port 0 Command Error
Port 0 FIS Configuration
Port 0 PCI(X) Request FIFO Threshold
Reserved
Port 0 8B/10B Decode Error Counter
Port 0 CRC Error Counter
Port 0 Handshake Error Counter
Reserved
Port PHY Configuration
Reserved
Port 0 Slot Status
Reserved
Command Activation Registers
Reserved
Port Context Register
Reserved
Port 0 SControl
Port 0 SStatus
Port 0 SError
Port 0 SActive (indirect location)
Reserved
Port 1 Registers mapped as above
Port 2 Registers mapped as above
Port 3 Registers mapped as above
Table 7-4 SiI3124 Internal Register Space – Base Address 1
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