參數(shù)資料
型號(hào)： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁(yè)數(shù)： 59/88頁(yè)
文件大小： 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Silicon Image, Inc.
7.1.17 MSI Message Data
Address Offset: 60
H
Access Type: Read/Write
Reset Value: 0x0000_0000
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
59
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Message Data
This register specifies the MSI Message Data. The register bits are defined below.
Bit [31:16]
: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit [15:00]
: Message Data (R/W) – This bit field specifies the Message Data for an MSI memory write
transaction.
7.1.18 Power Management Capability
Address Offset: 64
H
Access Type: Read Only
Reset Value: 0x0622_4001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
P
PME Support
P
Auxiliary
Current
D
R
P
PPM Rev
Next Capability Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:27]
: PME Support (R) – Power Management Event Support. This bit field is hardwired to 00
H
; the
SiI3124 does not support PME.
Bit [26]
: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1.
Bit [25]
: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1.
Bit [24:22]
: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 000
B
.
Bit [21]
: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the SiI3124
requires special initialization.
Bit [20]
: Reserved (R). This bit is reserved and returns zero on a read.
Bit [19]
: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0; the SiI3124 does not
support PME.
Bit [18:16]
: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010
B
to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
Bit [15:08]
: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired to 40
H
to point
to the 2
Capabilities register, the PCI-X Capability.
Bit [07:00]
: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 01
H
to indicate that this is a PCI
Power Management Capability.
7.1.19 Power Management Control + Status
Address Offset: 68
H
Access Type: Read/Write
Reset Value: 0x1900_2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
P
P
PPM Data Sel
P
Reserved
P
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