參數(shù)資料
型號(hào)： SII3124A
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁(yè)數(shù)： 68/88頁(yè)
文件大?。?/td> 621K
代理商： SII3124A
PCI-X to Serial ATA Controller
Data Sheet
7.3.1 Port LRAM
Address Offset: 000
H
-FFF
H
Access Type: Read/Write
Reset Value: indeterminate
The Port LRAM consists of 31 Slots of 128 bytes each and a 32
nd
“Slot” used to hold 16 Port Multiplier Device Specific
Registers.
Address Offset
Description
000
H
-07F
H
Slot 0
080
H
-0FF
H
Slot 1
100
H
-17F
H
Slot 2
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
68
180
H
-EFF
H
Slots 3-29
F00
H
-F7F
H
F80
H
-F83
H
F84
H
-F87
H
F88
H
-F8B
H
F8C
H
-F8F
H
Slot 30
Port Multiplier Device 0 Status Register
Port Multiplier Device 0 QActive Register
Port Multiplier Device 1 Status Register
Port Multiplier Device 1 QActive Register
F90
H
-FF7
H
Port Multiplier Device Registers for Devices 2-14
FF8
H
-FFB
H
FFC
H
-FFF
H
Port Multiplier Device 15 Status Register
Port Multiplier Device 15 QActive Register
Table 7-5 Port LRAM layout
Address Offset
000
H
-01F
H
020
H
-02F
H
030
H
-03F
H
040
H
-047
H
040
H
-07F
H
1C00
H
-1C07
H
Description
Current FIS and Control
Scatter/Gather Entry 0 or ATAPI command packet
Scatter/Gather Entry 1
Command Activation Register (Actual)
Scatter/Gather Table
Command Activation Register (Shadow)
Port Request
Block (PRB)
Table 7-6 Port LRAM Slot layout
A Port LRAM Slot is 128 bytes used to define Serial-ATA commands. The addresses shown above are for slot 0.
7.3.2 Port Slot Status
Address Offset: 1800
H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
A
Slot Status
This register provides the status for the 31 Command Slots for the Serial-ATA port. This register also appears along with the
Port Status register of the other 3 ports in Global register space. Reading this register will clear the Command Completion
Status for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control register is 0. The register bits are defined
below.
Bit [31]
: Attention (R) – This bit indicates that something occurred in the port that requires the attention of the host.
Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked
interrupt conditions reported in the Port Interrupt Status register.
Bit [30:0]
: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit is set when a command is transferred to the Slot RAM.
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